LTC4316
10
4316fa
For more information www.linear.com/LTC4316
OPERATION
N1, N2 and N3 are off, the READY pin is pulled low and
the quiescent current drops to 350μA.
Precharge and Hot Swap
When the LTC4316 is first powered on, switches N1 and
N2 are initially off. This allows a LTC4316 and its con
-
nected slaves
to be hot swapped onto an active I
2
C bus.
Internal precharge circuitry initially sets the bus lines to
1V through a 200k resistor, minimizing disturbance to an
active bus when the LTC4316 is connected. The LTC4316
keeps N1 and N2 off until ENABLE goes high, the XORL/
XORH pins are read, and both sides of the I
2
C bus are
idle (indicated either by a STOP bit or all bus pins high for
longer than 120μs). Once these conditions are met, N1
and N2 turn on, and the READY pin goes high to indicate
that the LTC4316 is ready to start address translation.
Pass-Through Mode
If the master wants to communicate with the slave us
-
ing the general call address, it can temporarily disable
address
translation by pulling XORH high. This disables
address translation and keeps N1 and N2 on regardless
of the activity on the buses. Any translation
that may be in
progress is stopped immediately when XORH goes high.
Extra Transitions on SDAOUT
In an I
2
C /SMBus system, the master changes the state of
the SDA line when SCL is low. The LTC4316 also advances
the address translation byte shift register when the SCLIN
is low. The translation byte transitions occur approximately
100ns after the falling edge of SCLIN. If the SDAIN tran
-
sitions sent
by the master do not coincide exactly with
the LTC4316 address translation bit transitions, an extra
transition
on SDAOUT may appear (Figure 7). These extra
SDA transitions are like glitches similar to those occurring
during normal Acknowledge bit transitions and do not pose
problems in the system because devices on the bus latch
SDA data only when SCL is high.
Level Translation and Supply Voltage Matching
The LTC4316 can operate with different supply voltages
on the input and output bus, and it will level shift the
voltages on the SCLIN, SDAIN, SCLOUT, and SDAOUT
pins to match the supply voltage at each side. V
CC
must
be powered from the lower of the two supply voltages
for level shifting to operate correctly. For example, if the
input bus is powered by
a 5V supply and the output bus
is powered by a 3.3V supply, the LTC4316 V
CC
pin must
be connected to the 3.3V supply as shown in Figure 8.
Figure 7. Extra Transitions on SDAOUT While SCL Is Low
SDAOUT
SCLIN
SDAIN
GLITCH
0 1 0 1
0 1 1 0
0 0 1 1
N2 GATE
N2 OFF
GLITCH
Figure 8. A 5V to 3.3V Level Translation Application
MASTER
SCLOUT
SDAOUT
SCLIN
SDAIN
SLAVE
#1
LTC4316
V
CC
If the LTC4316 supply pin is connected to the higher bus
supply, current may flow through the switches N1 and
N2 to the bus with lower supply. If the voltage difference
is less than 1V, this current is limited to less than 10μA.
This allows the input and output buses to be connected
to nominally identical supplies that may have up ±10%
tolerance, and the LTC4316 V
CC
pin can be connected to
either supply.
Extra START and STOP Bits
During normal operation, an I
2
C master should not issue
a START or STOP bit within a data byte. I
2
C slave behavior
when such a command is received can be unpredictable.
The LTC4316 will recover automatically when an unex
-
pected START or STOP is received during the address byte;
however, depending on the state of the translating bits,
