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MC100EPT21MNR4

P1-P3P4-P6P7-P9
© Semiconductor Components Industries, LLC, 2012
September, 2012 − Rev. 22
1 Publication Order Number:
MC100EPT21/D
MC100EPT21
3.3V Differential
LVPECL/LVDS/CML to
LVTTL/LVCMOS Translator
The MC100EPT21 is a Differential LVPECL/LVDS/CML to
LVTTL/LVCMOS translator. Because LVPECL (Positive ECL),
LVDS, and positive CML input levels and LVTTL/LVCMOS output
levels are used, only +3.3 V and ground are required. The small
outline 8−lead SOIC package makes the EPT21 ideal for applications
which require the translation of a clock or data signal.
The V
BB
output allows this EPT21 to be cap coupled in either
single−ended or differential input mode. When single−ended cap
coupled, V
BB
output is tied to the D input and D is driven for a
non−inverting buffer, or V
BB
output is tied to the D input and D is
driven for an inverting buffer. When cap coupled differentially, V
BB
output is connected through a resistor to each input pin. If used, the
V
BB
pin should be bypassed to V
CC
via a 0.01 mF capacitor. For
additional information see AND8020/D. For a single−ended direct
connection use an external voltage reference source such as a resistor
divider. Do not use V
BB
for a single−ended direct connection or port to
another device.
Features
• 1.4 ns Typical Propagation Delay
• Maximum Frequency > 275 MHz Typical
• LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
• 24 mA TTL outputs
• Operating Range: V
CC
= 3.0 V to 3.6 V with GND = 0 V
• The 100 Series Contains Temperature Compensation
• V
BB
Output
• These Devices are Pb−Free and are RoHS Compliant
MARKING
DIAGRAMS*
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
KA21
ALYWG
G
SO−8
D SUFFIX
CASE 751
TSSOP−8
DT SUFFIX
CASE 948R
1
8
1
8
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
KPT21
ALYW
G
1
8
1
8
DFN8
MN SUFFIX
CASE 506AA
(Note: Microdot may be in either location)
3RMG
G
1
MC100EPT21
http://onsemi.com
2
1
2
3
45
6
7
8
Q
GND
V
CC
Figure 1. Logic Diagram and 8−Lead Pinout (Top View)
D
NCD
V
BB
NC
LVTTL
LVPECL
Table 1. PIN DESCRIPTION
PIN
Q
D*, D*
Differential LVPECL/LVDS/CML Input
FUNCTION
LVTTL/LVCMOS Output
V
CC
V
BB
Output Reference Voltage
Positive Supply
GND Ground
NC No Connect
* Pin will default to 1/2 of V
CC
when left open.
EP
(DFN8 only) Thermal exposed pad must be
connected to a sufficient thermal conduit. Elec-
trically connect to the most negative supply
(GND) or leave unconnected, floating open.
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor D
50 kW
Internal Input Pulldown Resistor D
50 kW
Internal Input Pullup Resistor D, D
50 kW
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 1.5 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Level 1
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 81 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC100EPT21
http://onsemi.com
3
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Power Supply GND = 0 V 3.8 V
V
IN
PECL Input Voltage GND = 0 V V
I
V
CC
0 to 3.8 V
I
BB
V
BB
Sink/Source ± 0.5 mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SO−8
SO−8
190
130
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board SO−8 41 to 44 °C/W
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
T
sol
Wave Solder Pb
Pb−Free
< 2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
q
JC
Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 4. PECL INPUT DC CHARACTERISTICS V
CC
= 3.3 V, GND = 0.0 V (Note 3)
Symbol Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
V
IH
Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV
V
IL
Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV
V
BB
Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
1.2 3.3 1.2 3.3 1.2 3.3 V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current −150 −150 −150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input parameters vary 1:1 with V
CC
.
4. V
IHCMR
min varies 1:1 with GND, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the
differential input signal.
P1-P3P4-P6P7-P9

MC100EPT21MNR4

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Buy MC100EPT21MNR4
Manufacturer:
ON Semiconductor
Description:
IC TRNSLTR UNIDIRECTIONAL 8DFN
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