Detailed Description
Supply Voltages
The MAX6715A–MAX6729A/MAX6797A µP supervisory
circuits maintain system integrity by alerting the µP to
fault conditions. These ICs are optimized for systems
that monitor two or three supply voltages. The output-
reset state is guaranteed to remain valid while either
V
CC
1 or V
CC
2 is above 0.8V.
Threshold Levels
Input-voltage threshold level combinations are indicat-
ed by a two-letter code in the
Reset Voltage Threshold
Suffix Guide
(Table 1). Contact factory for availability of
other voltage threshold combinations.
Reset Outputs
The MAX6715A–MAX6729A/MAX6797A provide an
active-low reset output (RST) and the MAX6725A/
MAX6726A also provide an active-high (RST) output.
RST, RST, RST1, and RST2 are asserted when the volt-
age at either V
CC
1 or V
CC
2 falls below the voltage
threshold level, RSTIN drops below threshold, or MR is
pulled low. Once reset is asserted, it stays low for the
reset timeout period (see Table 2). If V
CC
1, V
CC
2, or
RSTIN goes below the reset threshold before the reset
timeout period is completed, the internal timer restarts.
The MAX6715A/MAX6717A/MAX6719A/MAX6721A/
MAX6723A/MAX6725A/MAX6727A/MAX6728A contain
open-drain reset outputs, while the MAX6716A/
MAX6718A/MAX6720A/MAX6722A/MAX6724A/
MAX6726A/MAX6729A/MAX6797A contain push-pull
reset outputs. The MAX6727A provides two separate
open-drain RST outputs driven by the same internal logic.
Manual-Reset Input
Many µP-based products require manual-reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic-low on MR
asserts the reset output. Reset remains asserted while
MR is low for the reset timeout period (t
RP
) after MR
returns high. This input has an internal 50k pullup
resistor to V
CC
1 and can be left unconnected if not
used. MR can be driven with CMOS logic levels, or with
open-drain/collector outputs. Connect a normally open
momentary switch from MR to GND to create a manual-
reset function; external debounce circuitry is not
required. If MR is driven from long cables or if the
device is used in a noisy environment, connect a 0.1µF
capacitor from MR to GND to provide additional noise
immunity.
Adjustable Input Voltage
The MAX6719A/MAX6720A and MAX6723A–MAX6727A
provide an additional input to monitor a third system volt-
age. The threshold voltage at RSTIN is typically 626mV.
Connect a resistor-divider network to the circuit as shown
in Figure 1 to establish an externally controlled threshold
voltage, V
EXT_TH
.
V
EXT_TH
= 626mV((R1 + R2)/R2)
Low-leakage current at RSTIN allows the use of large-
valued resistors resulting in reduced power consump-
tion of the system.
Watchdog Input
The watchdog monitors µP activity through the watch-
dog input (WDI). To use the watchdog function, con-
nect WDI to a bus line or µP I/O line. When WDI
remains high or low for longer than the watchdog time-
out period, the reset output asserts.
The MAX6721A–MAX6729A/MAX6797A include a dual-
mode watchdog timer to monitor µP activity. The flexi-
ble timeout architecture provides a long period initial
watchdog mode, allowing complicated systems to
complete lengthy boots, and a short period normal
watchdog mode, allowing the supervisor to provide
quick alerts when processor activity fails. After each
reset event (V
CC
power-up/brownout, manual reset, or
watchdog reset), there is a long initial watchdog period
of 35s minimum. The long watchdog period mode pro-
vides an extended time for the system to power-up and
fully initialize all µP and system components before
assuming responsibility for routine watchdog updates.
MAX6715A–MAX6729A/MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
10 ______________________________________________________________________________________
MAX6719A/
MAX6720A/
MAX6723A–
MAX6727A
V
EXT_TH
R1
R2
RSTIN
GND
Figure 1. Monitoring a Third Voltage
MAX6715A–MAX6729A/MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
______________________________________________________________________________________ 11
The normal watchdog timeout period (1.12s min)
begins after the first transition on WDI before the con-
clusion of the long initial watchdog period (Figure 2).
During the normal operating mode, the supervisor will
issue a reset pulse for the reset timeout period if the µP
does not update the WDI with a valid transition (high-to-
low or low-to-high) within the standard timeout period
(1.12s min).
Leave WDI unconnected to disable the watchdog timer.
The WDI unconnected-state detector uses a small
(200nA typ) current source. Therefore, do not connect
WDI to anything that will source more than 50nA.
Power-Fail Comparator
PFI is the noninverting input to a comparator. If PFI is
less than V
PFI
(626.5mV), PFO goes low. Common uses
for the power-fail comparator include monitoring prereg-
ulated input of the power supply (such as a battery) or
providing an early power-fail warning so software can
conduct an orderly system shutdown. It can also be
used to monitor supplies other than V
CC
1 or V
CC
2 by
setting the power-fail threshold with a resistor-divider, as
shown in Figure 3. PFI is the input to the power-fail com-
parator. The typical comparator delay is 2µs from PFI to
PFO. Connect PFI to ground of V
CC
1 if unused.
Ensuring a Valid Reset Output
Down to V
CC
= 0V
The MAX6715A–MAX6729A/MAX6797A are guaranteed
to operate properly down to V
CC
= 0.8V. In applications
that require valid reset levels down to V
CC
= 0V, use a
pulldown resistor at RST to ground. The resistor value
used is not critical, but it must be large enough not to
load the reset output when V
CC
is above the reset thresh-
old. For most applications, 100k is adequate. This con-
figuration does not work for the open-drain outputs of the
MAX6715A/MAX6717A/MAX6719A/MAX6721A/
MAX6723A/MAX6725A/MAX6727A/MAX6728A. For push-
pull, active-high RST output connect the external resistor
as a pullup from RST to V
CC
1.
1.12s MAX
t
WDI-NORMAL
1.12s MAX
t
WDI-STARTUP
35s MAX
V
TH
V
CC
WDI
RST
t
RP
Figure 2. Normal Watchdog Startup Sequence
MAX6728A/
MAX6729A/
MAX6797A
R1
R2
PFI
GND
V
IN
PFO
V
TRIP
= V
PFI
R1 + R2
R2
()
MAX6728A/
MAX6729A/
MAX6797A
R1
R2
PFI
GND
V
CC
V
IN
PFO
V
TRIP
= R2
(V
PFI
)
1
R1
1
R2
+-
V
CC
R1
[]
()
V
PFI
= 626.5mV
A)
B)
Figure 3. Using Power-Fail Input to Monitor an Additional
Power-Supply a) V
IN
is Positive b) V
IN
is Negative
MAX6715A–MAX6729A/MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 µP
Supervisory Circuits
12 ______________________________________________________________________________________
MAX6729A
V
EXT
R1
R3
R2
PFI
GND
PFO
A
V
GOOD
= DESIRED V
EXT
GOOD VOLTAGE THRESHOLD
V
FAIL
= DESIRED V
EXT
FAIL VOLTAGE THRESHOLD
V
OH
= V
CC
1 (FOR PUSH-PULL PFO)
R2 = 50k (FOR > 10µA R2 CURRENT)
R1 = R2 ((V
GOOD
- V
PFI
) - (V
PFI
)(V
GOOD
- V
FAIL
)/V
OH
)/V
PFI
R3 = (R1 x V
OH
)/(V
GOOD
- V
FAIL
)
V
GOOD
V
FAIL
V
IN
PFO
Figure 5. Adding Hysteresis to Power-Fail for Push-Pull PFO
Applications Information
Interfacing to µPs with Bidirectional
Reset Pins
Most µPs with bidirectional reset pins can interface
directly to open-drain RST output options. Systems
simultaneously requiring a push-pull RST output and a
bidirectional reset interface can be in logic contention.
To prevent contention, connect a 4.7k resistor
between RST and the µP’s reset I/O port as shown in
Figure 4.
Adding Hysteresis to the Power-Fail
Comparator
The power-fail comparator has a typical input hysteresis
of 3mV. This is sufficient for most applications where a
power-supply line is being monitored through an external
voltage-divider (see the
Power-Fail Comparator
section).
If additional noise margin is desired, connect a resistor
between PFO and PFI as shown in Figure 5. Select the
values of R1, R2, and R3 so PFI sees V
PFI
(626mV) when
V
EXT
falls to its power-fail trip point (V
FAIL
) and when V
IN
rises to its power-good trip point (V
GOOD
). The hysteresis
window extends between the specified V
FAIL
and V
GOOD
thresholds. R3 adds the additional hysteresis by sinking
current from the R1/R2 divider network when PFO is
logic-low and sourcing current into the network when PFO
is logic-high. R3 is typically an order of magnitude greater
than R1 or R2.
The current through R2 should be at least 2.5µA to ensure
that the 100nA (max) PFI input current does not signifi-
cantly shift the trip points. Therefore, R2 < V
PFI
/10µA <
62k for most applications. R3 will provide additional hys-
teresis for PFO push-pull (V
OH
= V
CC
1) or open-drain
(V
OH
= V
PULLUP
) applications.
Monitoring an Additional Power Supply
These µP supervisors can monitor either positive or
negative supplies using a resistor voltage-divider to
PFI. PFO can be used to generate an interrupt to the µP
or cause reset to assert (Figure 3).
Monitoring a Negative Voltage
The power-fail comparator can be used to monitor a
negative supply voltage using the circuit shown in
Figure 3. When the negative supply is valid, PFO is low.
When the negative supply voltage drops, PFO goes
high. The circuit’s accuracy is affected by the PFI
threshold tolerance, V
CC
, R1, and R2.
Negative-Going V
CC
Transients
The MAX6715A–MAX6729A/MAX6797A supervisors are
relatively immune to short-duration negative-going V
CC
transients (glitches). It is usually undesirable to reset
the µP when V
CC
experiences only small glitches. The
Typical Operating Characteristics
show Maximum
Transient Duration vs. Reset Threshold Overdrive, for
which reset pulses are not generated. The graph was
produced using negative-going V
CC
pulses, starting
above V
TH
and ending below the reset threshold by the
MAX6715A–
MAX6729A/
MAX6797A
GND GND
V
CC
1V
CC
2
V
CC
2
V
CC
1
RST
RESET TO OTHER SYSTEM COMPONENTS
RESET
µP
4.7k
Figure 4. Interfacing to µPs with Bidirectional Reset I/O

MAX6717AUKRVD6+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits Dual uPower Superviso
Lifecycle:
New from this manufacturer.
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