AT89C51RC-24PC Datasheet AT89C51RC-24JI, AT89C51RC-24AC, AT89C51RC-24PI | P10-P12

AT89C51RC

1920B–MICRO–11/02

accesses the SFR at location 0S0H (which is P2). Instructions that use indirect address-

ing access the Upper 128 bytes of data RAM. For example:

MOV@R0, # data

where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2

(whose address is 0A0H).

Note that stack operations are examples of indirect addressing, so the upper 128 bytes

of data RAM are available as stack space.

The 256 bytes of ERAM can be accessed by indirect addressing, with EXTRAM bit

cleared and MOVX instructions. This part of memory is physically located on-chip, logi-

cally occupying the first 256 bytes of external data memory.

Figure 1. Internal and External Data Memory Address

(with EXTRAM = 0)

With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in

combination with any of the registers R0, R1 of the selected bank or DPTR. An access

to ERAM will not affect ports P0, P2, P3.6 (WR

), and P3.7 (RD). For example, with

EXTRAM = 0,

MOVX@R0, # data

where R0 contains 0A0H, accesses the ERAM at address 0A0H rather than external

memory. An access to external data memory locations higher than FFH (i.e. 0100H to

FFFFH) will be performed with the MOVX DPTR instructions in the same way as in the

standard 80C51, i.e., with P0 and P2 as data/address bus, and P3.6 and P3.7 as write

and read timing signals. Refer to Figure 1.

With EXTRAM = 1, MOVX @ Ri and MOVX@DPTR will be similar to the standard

80C51. MOVX@Ri will provide an 8-bit address multiplexed with data on Port 0 and any

output port pins can be used to output higher-order address bits. This is to provide the

external paging capability. MOVX@DPTR will generate a 16-bit address. Port 2 outputs

the high-order 8 address bits (the contents of DP0H), while Port 0 multiplexes the low-

order 8 address bits (the contents of DP0L) with data. MOVX@Ri and MOVX@DPTR

will generate either read or write signals on P3.6 (WR

) and P3.7 (RD).

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and

upper RAM) internal data memory. The stack may not be located in the ERAM.

ERAM

256 BYTES

UPPER

128 BYTES

INTERNAL

RAM

LOWER

128 BYTES

INTERNAL

RAM

SPECIAL

FUNCTION

EXTERNAL

DATA

MEMORY

FFFF

0100

0000

AT89C51RC

1920B–MICRO–11/02

Hardware Watchdog

Timer

(One-time Enabled

with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be sub-

jected to software upsets. The WDT consists of a 13-bit counter and the WatchDog

Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To

enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST regis-

ter (SFR location 0A6H). When the WDT is enabled, it will increment every machine

cycle while the oscillator is running. The WDT timeout period is dependent on the exter-

nal clock frequency. There is no way to disable the WDT except through reset (either

hardware reset or WDT overflow reset). When WDT overflows, it will drive an output

RESET HIGH pulse at the RST pin.

Using the WDT To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST

writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 13-bit counter over-

flows when it reaches 8191 (1FFFH), and this will reset the device. When the WDT is

enabled, it will increment every machine cycle while the oscillator is running. This means

the user must reset the WDT at least every 8191 machine cycles. To reset the WDT the

user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The

WDT counter cannot be read or written. When WDT overflows, it will generate an output

RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where

TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sec-

tions of code that will periodically be executed within the time required to prevent a WDT

reset.

WDT During Power-

down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in

Power-down mode, the user does not need to service the WDT. There are two methods

of exiting Power-down mode: by a hardware reset or via a level-activated external inter-

rupt which is enabled prior to entering Power-down mode. When Power-down is exited

with hardware reset, servicing the WDT should occur as it normally does whenever the

AT89C51RC is reset. Exiting Power-down with an interrupt is significantly different. The

interrupt is held low long enough for the oscillator to stabilize. When the interrupt is

brought high, the interrupt is serviced. To prevent the WDT from resetting the device

while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.

It is suggested that the WDT be reset during the interrupt service for the interrupt used

to exit Power-down mode.

To ensure that the WDT does not overflow within a few states of exiting Power-down, it

is best to reset the WDT just before entering Power-down mode.

Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine

whether the WDT continues to count if enabled. The WDT keeps counting during IDLE

(WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the

AT89C51RC while in IDLE mode, the user should always set up a timer that will period-

ically exit IDLE, service the WDT, and reenter IDLE mode.

With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the

count upon exit from IDLE.

UART The UART in the AT89C51RC operates the same way as the UART in the AT89C51

and AT89C52. For further information, see the December 1997 Microcontroller Data

Book, page 2-48, section titled, “Serial Interface”.

AT89C51RC

1920B–MICRO–11/02

Timer 0 and 1 Timer 0 and Timer 1 in the AT89C51RC operate the same way as Timer 0 and Timer 1

in the AT89C51 and AT89C52.

Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter.

The type of operation is selected by bit C/T2

in the SFR T2CON (shown in Table 2).

Timer 2 has three operating modes: capture, auto-reload (up or down counting), and

baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3.

Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 reg-

ister is incremented every machine cycle. Since a machine cycle consists of 12

oscillator periods, the count rate is 1/12 of the oscillator frequency.

In the Counter function, the register is incremented in response to a 1-to-0 transition at

its corresponding external input pin, T2. In this function, the external input is sampled

during S5P2 of every machine cycle. When the samples show a high in one cycle and a

low in the next cycle, the count is incremented. The new count value appears in the reg-

ister during S3P1 of the cycle following the one in which the transition was detected.

Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 tran-

sition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given

level is sampled at least once before it changes, the level should be held for at least one

full machine cycle.

Capture Mode In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0,

Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit

can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same

operation, but a 1-to-0 transition at external input T2EX also causes the current value in

TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the

transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can

generate an interrupt. The capture mode is illustrated in Figure 2.

Auto-Reload (Up or

Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-

reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in

the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will

default to count up. When DCEN is set, Timer 2 can count up or down, depending on the

value of the T2EX pin.

Table 3. Timer 2 Operating Modes

RCLK +TCLK CP/RL2 TR2 MODE

0 0 1 16-bit Auto-reload

0 1 1 16-bit Capture

1 X 1 Baud Rate Generator

X X 0 (Off)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

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