22
AT89C51RC
1920B–MICRO–11/02
Programming the
Flash
The AT89C51RC is shipped with the on-chip Flash memory array ready to be pro-
grammed. The programming interface needs a high-voltage (12-volt) program enable
signal and is compatible with conventional third-party Flash or EPROM programmers.
The AT89C51RC code memory array is programmed byte-by-byte.
Programming Algorithm: Before programming the AT89C51RC, the address, data,
and control signals should be set up according to the Flash programming mode table
and Figures 10 and 11. To program the AT89C51RC, take the following steps:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA
/V
PP
to 12V.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The
byte-write cycle is self-timed and typically takes no more than 50 µs. Repeat
steps 1 through 5, changing the address and data for the entire array or until the
end of the object file is reached.
Chip Erase Sequence: Before the AT89C51RC can be reprogrammed, a Chip Erase
operation needs to be performed. To erase the contents of the AT89C51RC, follow this
sequence:
1. Raise V
CC
to 6.5V.
2. Pulse ALE/PROG once (duration of 200 ns - 500 ns) and wait for 150 ms.
3. Power V
CC
down and up to 6.5V.
4. Pulse ALE/PROG once (duration of 200 ns - 500 ns) and wait for 150 ms.
5. Power V
CC
down and up.
Data
Polling: The AT89C51RC features Data Polling to indicate the end of a write
cycle. During a write cycle, an attempted read of the last byte written will result in the
complement of the written data on P0.7. Once the write cycle has been completed, true
data is valid on all outputs, and the next cycle may begin. Data
Polling may begin any
time after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also be monitored by the
RDY/BSY
output signal. P3.0 is pulled low after ALE goes high during programming to
indicate BUSY
. P3.0 is pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed
code data can be read back via the address and data lines for verification. The status of
the individual lock bits can be verified directly by reading them back.
Reading the Signature Bytes: The signature bytes are read by the same procedure as
a normal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7
must be pulled to a logic low. The values returned are as follows:
(000H) = 1EH indicates manufactured by Atmel
(100H) = 51H
(200H) = 07H indicates 89C51RC
23
AT89C51RC
1920B–MICRO–11/02
Programming
Interface
Every code byte in the Flash array can be programmed by using the appropriate combi-
nation of control signals. The write operation cycle is self-timed and once initiated, will
automatically time itself to completion.
Most major worldwide programming vendors offer support for the Atmel microcontroller
series. Please contact your local programming vendor for the appropriate software
revision.
Notes: 1. Write Code Data requires a 200 ns PROG pulse.
2. Write Lock Bits requires a 100 µs PROG
pulse.
3. Chip Erase requires a 200 ns - 500 ns PROG
pulse.
4. RDY/BSY
signal is output on P3.0 during programming.
Table 8. Flash Programming Modes
Mode V
CC
RST PSEN
ALE/
PROG
EA/
V
PP
P2.6 P2.7 P3.3 P3.6 P3.7
P0.7-0
Data
P3.4 P2.5-0 P1.7-0
Address
Write Code Data 5V H L
(1)
12 VLHHHHD
IN
A14 A13-8 A7-0
Read Code Data 5V H L H
H/12
V
LLLHHD
OUT
A14 A13-8 A7-0
Write Lock Bit 1 6.5V H L
(2)
12 VHHHHH X X X X
Write Lock Bit 2 6.5V H L
(2)
12 V H H H L L X X X X
Write Lock Bit 3 6.5V H L
(2)
12 V H L H H L X X X X
Read Lock Bits
1, 2, 3
5V H L H H H H L H L
P0.2,
P0.3,
P0.4
XX X
Chip Erase 6.5V H L
(3)
12VHLHLL X X X X
Read Atmel ID 5V H L H H LLLLL1EHXXX 0000 00H
Read Device ID 5V H L H H LLLLL51HXXX 0001 00H
Read Device ID 5V H L H H LLLLL07HXXX 0010 00H
24
AT89C51RC
1920B–MICRO–11/02
Figure 10. Programming the Flash Memory
Figure 11. Verifying the Flash Memory
Note: *Programming address line A14 (P3.4) is not the same as the external memory address
line A14 (P2.6).
P1.0 - P1.7
P2.6
P3.6
P2.0 - P2.5
A0 - A7
ADDR.
0000H/7FFFH
SEE FLASH
PROGRAMMING
MODES TABLE
3 - 33 MHz
A14*
P0
4.5V to 5.5V
P2.7
PGM
DATA
PROG
V/V
IH PP
V
IH
ALE
P3.7
XTAL2 EA
RST
PSEN
XTAL
1
GND
V
CC
AT89C51RC
P3.4
P3.3
P3.0
RDY/
BSY
A8 - A13
P1.0 - P1.7
P2.6
P3.6
P2.0 - P2.5
A0 - A7
ADDR.
0000H/7FFFH
SEE FLASH
PROGRAMMING
MODES TABLE
3 - 33 MHz
P0
P2.7
PGM DATA
(USE 10K
PULL-UPS)
V
IH
V
IH
ALE
P3.7
XTAL2 EA
RST
PSEN
XTAL1
GND
V
CC
A14*
AT89C51RC
P3.4
P3.3
A8 - A13
4.5V to 5.5V

AT89C51RC-24PC

Mfr. #:
Manufacturer:
Description:
IC MCU 8BIT 32KB FLASH 40PDIL
Lifecycle:
New from this manufacturer.
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