5
FN6141.1
August 5, 2015
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Principles of Operation
The ISL88016 and ISL88017 devices provides a low cost
solution for those voltage monitoring applications needing
supply voltage supervision with power reset control, and
manual reset assertion. By integrating these common
features along with three pins of Vth programming into a
small 6 Ld TSOT-23 package and using only 1µA of supply
current, the ISL88016 and ISL88017 devices can lower
system cost, reduce board space requirements, and
increase the reliability of a system while reducing inventory
overhead costs.
Low Voltage Monitoring
During normal operation, the ISL88016 and ISL88017
monitor the voltage level of V
DD
. The device asserts a reset
(RST
= LOW) if this voltage is less than the programmed
voltage trip point. The reset signal prevents system
operation during a power failure or brownout condition. This
reset signal remains asserted until V
DD
exceeds the voltage
threshold setting for the reset time delay period t
POR
. (See
Figure 1).
The ISL88016 and ISL88017 allow users to customize the
Power-On Reset voltage threshold level, which is the voltage
at which the reset is deasserted. The three VSET inputs are
either tied to V
DD
, GND or left open to program V
TH
. See
the Power-On Reset Voltage Setting table on page 3 for
specific voltage configuration. Also see Figure 2 for a
schematic representation of the VSET pins being
programmed, noting the minimum necessary components
for IC operation. Do not attempt to reprogram a V
TH
while
the IC is biased.
Power-On Reset (POR)
Applying power to the ISL88016 and ISL88017 activates a
POR circuit which asserts reset once V
DD
= 1 V. (i.e., RST
goes LOW). This provides several benefits:
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
• It prevents the processor from operating prior to
stabilization of the oscillator.
• It ensures that the monitored device is held out of
operation until internal registers are properly loaded.
• It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
The reset signal remains asserted until V
DD
rises above the
minimum voltage sense level for time period t
POR
. This
ensures that the V
DD
voltage has stabilized.
Optional V
DD
de-coupling capacitance can be added to filter
transients if needed.
FIGURE 1. VOLTAGE MONITORING TIMING DIAGRAM
V
DD
MR
V
TH /
V
POR
1V
>t
MR
RST
t
POR
t
POR
t
POR
t
RST
ISL88016
VSET1
ISL88017
FIGURE 2. SETTING V
POR
USING VSET INPUTS
VSET2
VSET3GND
V
DD
RST/MR
ISL88016, ISL88017
