IRS2168DPBF Datasheet IRS2168DSTRPBF, IRS2168DSPBF, IRS2168DPBF | P13-P15

IRS2168D(S)PbF

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ignition voltage) of the ballast output stage. Should this

voltage exceed the internal threshold of 1.2 V (V

CSTH+),

the

ignition regulation circuit controls the voltage on the VCO

pin to increase the frequency slightly (see Fig. 6). This

cycle-by-cycle feedback from the C

pin to the VCO pin

will adjust the frequency each cycle to limit the amplitude

of the current for the entire duration of ignition mode.

VCO

1.25V

Figure 6:

Ignition regulation timing diagram

When C

exceeds 2/3*V

CPHRUN+

) for the second

time, the IC enters run mode and the fault counter

becomes enabled. The ignition regulation disabled in run

mode but the IC will enter fault mode after 65 (n

EVENTS

)

consecutive over-current faults and gate driver outputs

HO, LO and PFC will be latched low.

The output voltage of the ballast will increase during the

ignition ramp t

RAMP

because the frequency ramp down

from the preheat frequency to the ignition frequency and

will be constant during ignition because the ignition

regulation circuit will regulate the amplitude of the current

for the entire duration of the ignition time t

IGN

(Figs. 7 and

8).

During ignition mode, the PFC circuit is working in high-

gain mode and keeps the DC bus voltage regulated at a

constant level. The high-gain mode is necessary to

prevent the DC bus from decreasing during lamp ignition

or ignition regulation. Also during ignition mode, the

SD/EOL fault is disabled.

tPH tIGN

tRAMP

VOUT

VCPH

Figure 7: Ballast output voltage and CPH pin during

preheat and ignition with deactivated lamp, time span

100ms

tIGN

tRAMP

VOUT

VCPH

Figure 8: Ballast output voltage and CPH pin during

preheat and ignition with deactivated lamp, time span

50ms

IRS2168D(S)PbF

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Run Mode (RUN)

Once V

has exceeded 2/3*V

CPHRUN+

) for the

second time, the IC enters run mode. CPH continues to

charge up to V

. The operating frequency is at the

minimum frequency (after the ignition ramp) and is

programmed by the external resistor (R

FMIN

) at the FMIN

pin. Should hard-switching occur at the half-bridge at any

time (open-filament, lamp removal, etc.), the voltage

across the current sensing resistor (R

) will exceed the

internal threshold of 1.2 V (V

CSTH+

) and the fault counter

will begin counting (see Fig. 5). Should the number of

consecutive over-current faults exceed 65 (n

EVENTS

), the

IC will enter fault mode and the HO, LO and PFC gate

driver outputs will be latched low. During run mode, the

end-of-life (EOL) window comparator and the DC bus

undervoltage reset are both enabled.

DC Bus Undervoltage Reset

Should the DC bus decrease too low during a brown-out

line condition or over-load condition, the resonant output

stage to the lamp can shift near or below resonance. This

can produce hard switching at the half- bridge that can

damage the half-bridge switches, or, the DC bus can

decrease too far and the lamp can

extinguish. To protect

against this, the V

BUS

pin includes a 3.0 V undervoltage

reset threshold V

BUSUV-

. When the IC is in run mode and

the voltage at the V

BUS

pin decreases below 3.0 V (V

BUSUV-

), V

will be discharged through an internal MOSFET

down to the V

CCUV-

threshold and all gate driver outputs

will be latched low. For proper ballast design, the

designer should set the over-current limit of the PFC

section such that the DC bus does not drop until the AC

line input voltage falls below the minimum rated

input

voltage of the ballast (see PFC section). When the PFC

over-current limit is correctly set, the DC bus voltage will

start to decrease when over-current is reached during

low-line conditions. The voltage measured at the V

BUS

will decrease below the internal 3.0 V threshold V

BUSUV-

and the ballast will turn off cleanly. The pull-up resistor to

VCC

) will then turn the ballast on again when the AC

input line voltage increases high enough again where

exceeds V

CCUV+

. R

VCC

should be set to turn the ballast on

at the minimum specified ballast input voltage and the

PFC over-current should be set somewhere below this

level. This hysteresis will result in clean turn-on and turn-

off of the ballast.

SD/EOL and CS Fault Mode

Should the voltage at the SD/EOL pin exceed 3.0 V

EOLTH+)

or decrease below 1.0 V (V

EOLTH-

) during run

mode, an end-of-life (EOL) fault condition has occurred

and the IC enters fault mode. LO, HO and PFC gate

driver outputs are all latched off in the ‘low’ state. CPH is

discharged to COM for resetting the preheat time and

VCO is discharged to COM for resetting the frequency.

To exit fault mode, V

can be decreased below V

CCUV-

(ballast power off) or the SD pin can be increased above

5.0 V (V

SDTH+

) (lamp removal). Either of these will force

the IC to enter UVLO mode (see State Diagram, page 3).

Once V

is above V

CCUV+

(ballast power on) and SD is

pulled above 5.0 V (V

SDTH+

) and back below 3.0 V (V

SDTH-

)

(lamp re-insertion), the IC will enter preheat mode and

begin oscillating again.

The current sense function will force the IC to enter fault

mode only after the voltage at the CS pin has been

greater than 1.2 V (V

CSTH+

) for 65 (n

EVENTS

) consecutive

cycles of LO. The voltage at the CS pin is AND-ed with

LO (see Fig. 9) so it will work with pulses that occur

during the LO on-time or DC. If the over-current faults

are not consecutive, then the internal fault counter will

count back down each cycle when there is no fault.

Should an over-current fault occur only for a few cycles

and then not occur again, the counter will eventually reset

to zero. The over-current fault counter is enabled during

preheat and run modes and disabled during ignition

mode.

50 Cycles

Run or Preheat Mode

Fault Mode

1.25V

Figure 9: Fault counter timing diagram

IRS2168D(S)PbF

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II. PFC Section

Functional Description

In most electronic ballasts it is necessary to have the

circuit act as a pure resistive load to the AC input line

voltage. The degree to which the circuit matches a pure

resistor is measured by the phase shift between the input

voltage and input current and how well the shape of the

input current waveform matches the shape of the

sinusoidal input voltage. The cosine of the phase angle

between the input voltage and input current is defined as

the power factor (PF), and how well the shape of the input

current waveform matches the shape of the input voltage

is determined by the total harmonic distortion (THD). A

power factor of 1.0 (maximum) corresponds to zero

phase shift and a THD of 0% and represents a pure

sinusoidal waveform (no distortion). For this reason it is

desirable to have a high PF and a low THD. To achieve

this, the IRS2168D includes an active power factor

correction (PFC) circuit.

The control method implemented in the IRS2168D is for a

boost-type converter (Fig. 10) running in critical-

conduction mode (CCM). This means that during each

switching cycle of the PFC MOSFET, the circuit waits

until the inductor current discharges to zero before turning

the PFC MOSFET on again. The PFC MOSFET is turned

on and off at a much higher frequency (>10 kHz) than the

line input frequency (50 to 60 Hz).

CBUS

(+)

(-)

MPFC

LPFC

DPFC

DC Bus

Figure 10:

Boost converter circuit

When the switch M

PFC

is turned on, the inductor L

PFC

connected between the rectified line input (+) and (-)

causing the current in L

PFC

to charge up linearly. When

PFC

is turned off, L

PFC

is connected between the rectified

line input (+) and the DC bus capacitor C

BUS

(through

diode D

PFC

) and the stored current in L

PFC

flows into C

BUS

PFC

is turned on and off at a high frequency and the

voltage on C

BUS

charges up to a specified voltage. The

feedback loop of the IRS2168D regulates this voltage to a

fixed value by continuously monitoring the DC bus

voltage and adjusting the on-time of M

PFC

accordingly.

For an increasing DC bus the on-time is decreased, and

for a decreasing DC bus the on-time is increased. This

negative feedback control is performed with a slow loop

speed and a low loop gain such that the average inductor

current smoothly follows the low-frequency line input

voltage for high power factor and low THD. The on-time

of M

PFC

therefore appears to be fixed (with an additional

modulation to be discussed later) over several cycles of

the line voltage. With a fixed on-time, and an off-time

determined by the inductor current discharging to zero,

the result is a system where the switching frequency is

free-running and constantly changing from a high

frequency near the zero crossing of the AC input line

voltage, to a lower frequency at the peaks (Fig. 11).

V, I

Figure 11:

Sinusoidal line input voltage (solid line),

triangular PFC Inductor current and smoothed sinusoidal

line input current (dashed line) over one half-cycle of the

AC line input voltage

When the line input voltage is low (near the zero

crossing), the inductor current will charge up to a small

amount and the discharge time will be fast resulting in a

high switching frequency. When the input line voltage is

high (near the peak), the inductor current will charge up to

a higher amount and the discharge time will be longer

giving a lower switching frequency.

The PFC control circuit of the IRS2168D (Fig. 12)

includes five control pins: V

BUS

, COMP, ZX, PFC and OC.

The V

BUS

pin measures the DC bus voltage via an

external resistor voltage divider. The COMP pin programs

the on-time of M

PFC

and the speed of the feedback loop

with an external capacitor. The ZX pin detects when the

inductor current discharges to zero each switching cycle

using a secondary winding from the P

inductor. The P

pin is the low-side gate driver output for the external

MOSFET, M

PFC

. The OC pin senses the current flowing

through M

PFC

and performs cycle-by-cycle over-current

protection.

RVBUS1

RVBUS2

RVBUS

CCOMP

LPFC

MPFC

RPFC

DFPC

CBUS

(+)

(-)

RZX

PFC

Control

VBUS

COMP

PFC

COM

ROC

Figure 12:

IRS2168D simplified PFC control circuit

The V

BUS

pin is regulated against a fixed internal 4.0 V

reference voltage for regulating the DC bus voltage (Fig.

13). The feedback loop is performed by an operational

transconductance amplifier (OTA) that sinks or sources a

current to the external capacitor at the COMP pin. The

resulting voltage on the COMP pin sets the threshold for

the charging of the internal timing capacitor (C1, Figure

13) and therefore programs the on-time of M

PFC

. During

preheat and ignition modes of the ballast section, the gain

of the OTA is set to a high level to raise the DC bus level

quickly and to minimize the transient on the DC bus that

can occur during ignition. During run mode, the gain is

then decreased to a lower level necessary for a slower

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

IRS2168DPBF

Mfr. #:

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Gate Drivers Advanced PFC & Ballast Cntrl IC

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IRS2168DPBF

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