IRS2168D(S)PbF
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loop speed for achieving high power factor and low THD.
6
5
1
Q
S
RQ
2.0V
VBUS
COMP
ZX
5.1V
4.0V
GAI N
OTA1
4.3V
7
PFC
QS
R2 Q
R1
COMP3
COMP4
COMP5
RS3
RS4
VCC
Run Mode Signal
Fault Mode Signal
M1
WATCH
DOG
TIMER
M2
C1
3.0V
Discharge
VCC to
UVLO-
COMP2
8
OC
1.2V
Figure 13:
IRS2168D detailed PFC control circuit
The off-time of M
PFC
is determined by the time it takes the
L
PFC
current to discharge to zero. The zero current level
is detected by a secondary winding on LPFC that is
connected to the ZX pin through an external current
limiting resistor R
ZX
. A positive-going edge exceeding the
internal 2 V threshold (V
ZXTH+
) signals the beginning of the
off-time. A negative-going edge on the ZX pin falling
below 1.7 V (V
ZXTH+
- V
ZXHYS
) will occur when the L
PFC
current discharges to zero which signals the end of the
off-time and M
PFC
is turned on again (Fig. 14). The cycle
repeats itself indefinitely until the PFC section is disabled
due to a fault detected by the ballast section (Fault
Mode), an over-voltage or undervoltage condition on the
DC bus, or, the negative transition of ZX pin voltage does
not occur. Should the negative edge on the ZX pin not
occur, M
PFC
will remain off until the watch-dog timer forces
a turn-on of M
PFC
for an on-time duration programmed by
the voltage on the COMP pin. The watch-dog pulses
occur every 400 µs (t
WD
) indefinitely until a correct
positive- and negative-going signal is detected on the ZX
pin and normal PFC operation is resumed. Should the
OC pin exceed the 1.2 V (V
OCTH+
) over-current threshold
during the on-time, the PFC output will turn off. The
circuit will then wait for a negative-going transition on the
ZX pin or a forced turn-on from the watch-dog timer to
turn the PFC output on again.
I
LPFC
PFC
ZX
OC
1.2V
. . .
. . .
. . .
. . .
Figure 14: Inductor current, PFC pin, ZX pin and OC pin
timing diagram
On-time Modulation Circuit
A fixed on-time of M
PFC
over an entire cycle of the line
input voltage produces a peak inductor current which
naturally follows the sinusoidal shape of the line input
voltage. The smoothed averaged line input current is in
phase with the line input voltage for high power factor but
the total harmonic distortion (THD), as well as the
individual higher harmonics, of the current can still be too
high. This is mostly due to cross-over distortion of the
line current near the zero-crossings of the line input
voltage. To achieve low harmonics that are acceptable to
international standard organizations and general market
requirements, an additional on-time modulation circuit has
been added to the PFC control. This circuit
dynamically
increases the on-time of M
PFC
as the line input voltage
nears the zero-crossings (Fig. 15). This causes the peak
L
PFC
current, and therefore the smoothed line input
current, to increase slightly higher near the zero-
crossings of the line input voltage. This reduces the
amount of cross-over distortion in the line input current
which reduces the THD and higher harmonics to low
levels.
0
0
I
LPFC
PFC
pin
near peak region of
rectified AC line
near zero-crossing region
of rectified AC line
Figure 15: On-time modulation circuit timing diagram
DC Bus Over-voltage Protection
Should over-voltage occur on the DC bus and the VBUS
pin exceeds the internal 4.3 V threshold (V
BUSOV+
), the
PFC output is disabled (set to a logic ‘low’). When the
DC bus decreases again and the V
BUS
pin decreases
below the internal 4.15 V threshold (V
BUSOV-
), a watch-dog
pulse is forced on the PFC pin and normal PFC operation
is resumed.
DC Bus Undervoltage Reset
When the input line voltage decreases, the on-time of
M
PFC
increases to keep the DC bus constant. The on-
time will continue to increase as the line voltage
continues to decrease until the OC pin exceeds the
internal 1.2 V over-current threshold (V
OCTH+
). At this
time, the on-time can no longer increase and the PFC can
no longer supply enough current to keep the DC bus fixed
for the given load power. This will cause the DC bus to
begin to decrease. The decreasing DC bus will cause the
V
BUS
pin to decrease below the internal 3.0 V threshold
(V
BUSUV-
) (Fig. 12).
