Document #: 001-55636 Rev. ** Page 5 of 11
Switching Characteristics
Over the Operating Range
[5]
Parameter Description
70 ns
Unit
Min Max
Read Cycle
t
RC
Read Cycle Time 70 ns
t
AA
Address to Data Valid 70 ns
t
OHA
Data Hold from Address Change 10 ns
t
ACE
CE LOW to Data Valid 70 ns
t
DOE
OE LOW to Data Valid 35 ns
t
LZOE
OE LOW to Low Z
[
6
]
5ns
t
HZOE
OE HIGH to High Z
[
7
]
25 ns
t
LZCE
CE LOW and to Low Z
[
6
]
10 ns
t
HZCE
CE HIGH to High Z
[
6, 7
]
25 ns
t
PU
CE
1
LOW and CE
2
HIGH to Power Up 0 ns
t
PD
CE
1
HIGH and CE
2
LOW to Power Down 70 ns
Write Cycle
[8, 9]
t
WC
Write Cycle Time 70 ns
t
SCE
CE
1
LOW and CE
2
HIGH
to Write End 60 ns
t
AW
Address Setup to Write End 60 ns
t
HA
Address Hold from Write End 0 ns
t
SA
Address Setup to Write Start 0 ns
t
PWE
WE Pulse Width 50 ns
t
SD
Data Setup to Write End 30 ns
t
HD
Data Hold from Write End 0 ns
t
HZWE
WE LOW to High Z
[
6, 7
]
25 ns
t
LZWE
WE HIGH to Low Z
[
6
]
10 ns
Notes
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V
CC(typ.)
, and output loading of the specified
I
OL
/I
OH
and 30 pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle #3 (WE
controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
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