PDF: 09005aef8085081a/Source: 09005aef806e129d Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD4C16_32x64A.fm - Rev. E 11/08 EN
11 ©2003 Micron Technology, Inc. All rights reserved.
128MB, 256MB (x64, SR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
Table 11: Idd Specifications and Conditions – 256MB
Values are for the MT46V16M16 DDR SDRAM only and are computed from values specified in the
512Mb (32 Meg x 16) component data sheet
Parameter/Condition Symbol -40B -335 -262
-26A/
-265
Units
Operating one device bank active-precharge current:
t
RC =
t
RC
(MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two clock cycles
Idd0 620 520 520 460 mA
Operating one device bank active-read-precharge current:
Burst = 4;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Iout = 0mA; Address and
control inputs changing once per clock cycle
Idd1 780 640 640 580 mA
Precharge power-down standby current: All device banks idle; Power-
down mode;
t
CK =
t
CK (MIN); CKE = LOW
Idd2P20 202020mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN);
CKE = HIGH; Address and other control inputs
changing once per clock
cycle;
Vin
=
Vref
for DQ, DQS, and DM
Idd2F 220 180 180 160 mA
Active power-down standby current: One device bank active; Power-
down mode;
t
CK =
t
CK (MIN); CKE = LOW
Idd3P 180 140 140 120 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
Idd3N 240 200 200 180 mA
Operating burst read current: Burst = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle;
t
CK =
t
CK (MIN); Iout = 0mA
Idd4R 840 660 660 580 mA
Operating burst write current: Burst = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
cycle
Idd4W 860 780 640 540 mA
Auto refresh current
t
RFC =
t
RFC (MIN)
Idd5 1380 1160 1160 1120 mA
t
RFC = 7.8125µs
Idd5A44 404040mA
Self refresh current: CKE ≤ 0.2V
Idd6 24 20 20 20 mA
Operating bank interleave read current: Four device bank
interleaving READs (burst = 4) with auto precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address and control inputs change only during active
READ or WRITE commands
Idd7 1920 1620 1600 1400 mA
