NCV898031
www.onsemi.com
8
APPLICATION INFORMATION
Current Mode Control
The NCV898031 incorporates a current mode control
scheme, in which the PWM ramp signal is derived from the
power switch current. This ramp signal is compared to the
output of the error amplifier to control the on−time of the
power switch. The oscillator is used as a fixed−frequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and the error amplifier, which is commonly
found in voltage mode controllers. The second benefit
comes from inherent pulse−by−pulse current limiting by
merely clamping the peak switching current. Finally, since
current mode commands an output current rather than
voltage, the filter offers only a single pole to the feedback
loop. This allows for a simpler compensation.
The NCV898031 also includes a slope compensation
scheme in which a fixed ramp generated by the oscillator is
added to the current ramp. A proper slope rate is provided to
improve circuit stability without sacrificing the advantages
of current mode control.
Current Limit
The NCV898031 features two current limit protections,
peak current mode and over current latch off. When the
current sense amplifier detects a voltage above the peak
current limit between ISNS and GND after the current limit
leading edge blanking time, the peak current limit causes the
power switch to turn off for the remainder of the cycle. Set
the current limit with a resistor from ISNS to GND, with R
=
V
CL
/ I
limit
.
If the voltage across the current sense resistor exceeds the
over current threshold voltage, the device enters over
current hiccup mode. The device will remain off for the
hiccup time and then go through the soft−start procedure.
Short Circuit Protection
If the short circuit enable bit is set (SCE = Y), the device
will attempt to protect the power MOSFET from damage.
When the output voltage falls below the short circuit trip
voltage, after the initial short circuit blanking time, the
device enters short circuit latch−off. The device will remain
off for the hiccup time and then go through the soft−start.
Enable
The Enable pin has two modes. When a DC logic high
(CMOS/TTL compatible) voltage is applied to this pin, the
NCV898031 operates at the programmed frequency. When
a DC logic low voltage is applied, the NCV898031 enters a
low quiescent current sleep mode. The NCV898031
requires 2 clock cycles after the falling edge of the Enable
signal to stop switching.
If the VIN pin voltage falls below V
UVLO
when EN pin is
at logic−high, the IC may not power up when VIN returns
back above the UVLO. To resume a normal operating state,
the EN pin must be cycled with a single logic−low to
logic−high transition.
UVLO
Input Undervoltage Lockout (UVLO) is provided to
ensure that unexpected behavior does not occur when VIN
is too low to support the internal rails and power the
controller. The IC will start up when enabled and VIN
surpasses the UVLO threshold plus the UVLO hysteresis
and will shut down when VIN drops below the UVLO
threshold or the part is disabled.
To avoid any lock state under UVLO conditions, the EN
pin should be in logic−low state. For further details, please
refer to Enable paragraph.
Internal Soft-Start
To insure moderate inrush current and reduce output
overshoot, the NCV898031 features a soft start which
charges a capacitor with a fixed current to ramp up the
reference voltage.
VDRV
An internal regulator provides the drive voltage for the
gate driver. Bypass with a ceramic capacitor to ground to
ensure fast turn on times. The capacitor should be between
0.1 mF and 1 mF, depending on switching speed and charge
requirements of the external MOSFET.
GDRV
An R
GND
= 15 kW (typical) GDRV−GND resistor is
strongly recommended.
