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ADV7533BCBZ-RL7

P1-P3P4-P6P7-P9P10-P12P13-P13
Data Sheet ADV7533
Rev. A | Page 3 of 12
FUNCTIONAL BLOCK DIAGRAM
AUDIO
DATA
CAPTURE
CEC
CONTROLLER
BUFFER
HDCP
ENCRYPTION
HDCP KEYS
N/V MEMORY
CEC_CLK
CEC
SPDIF/I2S
LRCLK
SCLK/MCLK
HDCP AND
EDID
MICRO-
CONTROLLER
DDC_SCL
DDC_SDA
SDA
SCL
HPD
INT
CTRL
ADV7533
SYNC
ADJUST
AND
GENERATION
DRx0
DRx1
DRxC
DRx2
2
2
2
2
HDMI_Tx0
HDMI_Tx1
HDMI_Tx2
HDMI_TxC
HDMI
TMDS
Tx
DSI
DECODE
POWER
AVDD
DVDD
A2VDD
V1P2
GND
V3P3
PD
COLOR
SPACE
CONVERTER
R_EXT
PVDD
DRx3
2
2
2
2
2
UP/
DOWN
DITHER
PATTERN
GENERATOR
BAND
GAP
I
2
C
SLAVE
I
2
C
MASTER
4 CH
DPHY
09821-001
Figure 1.
ADV7533 Data Sheet
Rev. A | Page 4 of 12
SPECIFICATIONS
Table 1. Electrical Specifications
Parameter Conditions Temp
Test
Level
1
ADV7533BCBZ
Min Typ Max Unit
DIGITAL INPUTS
Data Inputs—Audio, CEC_CLK
Input Voltage, High (V
IH
) Full VI 1.4 3.5 V
Input Voltage, Low (V
IL
) Full VI −0.3 +0.7 V
Input Capacitance 25°C VIII 1.0 1.5 pF
I
2
C Lines (SDA, SCL)
Input Voltage, High (V
IH
) Full VI 1.3 5.5 V
Input Voltage, Low (V
IL
) Full VI −0.3 +0.6 V
I
2
C Lines (DDCSDA, DDCSCL)
Input Voltage, High (V
IH
) Default values Full VI 1.3 5.5 V
Input Voltage, Low (V
IL
) Full VI −0.3 +0.6 V
Input Voltage, High (V
IH
) Programmable optional values Full IV 3.5 5.5 V
Input Voltage, Low (V
IL
) Full IV −0.5 +1.2 V
CEC
Input Voltage, High (V
IH
) Full VI 2.0 V
Input Voltage, Low (V
IL
) Full VI 0.6 V
Output Voltage, High (V
OH
) Full VI 2.5 3.63 V
Output Voltage, Low (V
OL
) Full VI −0.3 +0.6 V
HPD
Input Voltage, High (V
IH
) Full VI 1.3 5.5 V
Input Voltage, Low (V
IL
) Full VI −0.3 +0.6 V
DIGITAL OUTPUTS—INT
Output Voltage, Low (V
OL
) Load = 5 pF Full VI 0.4 V
THERMAL CHARACTERISTICS
Thermal Resistance
θ
JC
Junction-to-Case Full V 20 °C/W
θ
JA
Junction-to-Ambient Full V 43 °C/W
Ambient Temperature Full V −10 +25 +85 °C
DC SPECIFICATIONS
Input Leakage Current, I
IL
25°C VI −1 +1 μA
POWER SUPPLY
1.8 V Supply Voltage (DV
DD
, AV
DD
, A2V
DD
,
PV
DD
)
Full IV 1.71 1.8 1.9 V
V1P2 = (1.2 V) Full IV 1.14 1.2 1.26 V
V1P2 = (1.8 V) Full IV 1.71 1.8 1.9 V
Supply Voltage Noise Limit
DVDD —Digital I/O Pad Logic Full IV 64 mV rms
AVDD—HDMI Analog Core Full IV 64 mV rms
V1P2—HDMI/DSI Digital Core
1.2 V
Full
IV
43
mV rms
1.8 V Full Iv 64 mV rms
A2VDD—MIPI DPHY Full IV 64 mV rms
PVDD—HDMI PLL Refer to Figure 2 Full IV mV rms
3.3 V Supply Voltage (V3P3) Full IV 3.15 3.30 3.45 V
3.3 V Supply Voltage Noise Limit Full IV 64 mV rms
Power-Down Current
25°C VI 15 μA
Operating Current
DVDD I/O pads (30 bits at 720p) Full IV 6 mA
Data Sheet ADV7533
Rev. A | Page 5 of 12
Parameter Conditions Temp
Test
Level
1
ADV7533BCBZ
Min Typ Max Unit
AVDD HDMI analog core (24 bits at
720p)
Full IV 11 mA
V1P2 (1.2 V) HDMI/DSI digital core (DSI 30
bits/HDMI 24 bits at 720p)
Full IV 39 mA
A2VDD MIPI DPHY (30 bits/three
lanes/720p)
Full IV 12 mA
PVDD HDMI PLL (24 bits at 720p) Full IV 11 mA
V3P3—HDMI/HDCP Memory HDMI HDCP memory Full IV 0.3 mA
Transmitter Total Power 720p, 30-bit DSI in; 720p, 36-bit
HDMI out; typical random
pattern with CSC enabled,
HDCP enabled, audio enabled
V1P2 = 1.2 V Full IV 120 154 mW
V1P2 = 1.8 V Full VI 204 mW
AC SPECIFICATIONS
TMDS Output Clock Frequency 25°C IV 20 112 MHz
TMDS Output Clock Duty Cycle
25°C
IV
48
52
%
TMDS Differential Swing 25°C VII 800 1000 1200 mV
Differential Output Timing
Low-to-High Transition Time 25°C VII 75 175 ps
High-to-Low Transition Time 25°C VII 75 175 ps
AUDIO AC TIMING
2
SCLK Duty Cycle
When N = Even Number Full IV 40 50 60 %
When N = Odd Number Full IV 49 50 51 %
I
2
S, S/PDIF Setup, t
ASU
Full IV 2 ns
I
2
S, S/PDIF Hold Time, t
AHLD
Full IV 2 ns
LRCLK Setup Time, t
ASU
Full IV 2 ns
LRCLK Hold Time, t
AHLD
Full IV 2 ns
CEC
CEC_CLK Frequency
3
Full VIII 3 12 100 MHz
CEC_CLK Accuracy Full VIII −2 +2 %
CEC_CLK Duty Cycle Full VIII 40 60 %
I
2
C INTERFACE
SCL Clock Frequency Full VIII 400
4
kHz
SDA Setup Time, t
DSU
Full VIII 100 ns
SDA Hold Time, t
DHO
Full VIII 100 ns
Setup for Start, t
STASU
Full VIII 0.6 μs
Hold Time for Start, t
STAH
Full VIII 0.6 μs
Setup for Stop, t
STOSU
Full VIII 0.6 μs
Bus Free Between Stop and Start, t
BUF
Full VIII 1.3 μs
SCL High, t
HIGH
Full VIII 0.6 μs
SCL Low, t
LOW
Full VIII 1.3 μs
1
See the Explanation of Test Levels section.
2
12 MHz crystal for default register settings.
3
Only applies to S/PDIF if external MCLK is used.
4
I
2
C data rates of 100 KHz and 400 KHz are supported.
P1-P3P4-P6P7-P9P10-P12P13-P13

ADV7533BCBZ-RL7

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Buy ADV7533BCBZ-RL7
Manufacturer:
Analog Devices Inc.
Description:
Video ICs HDMI & NDA required see product comment
Lifecycle:
New from this manufacturer.
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