MAX188ACWP+ Datasheet MAX186DCAP+, MAX186AEPP+, MAX186CCAP+ | P13-P15

Internal Clock

In internal clock mode, the MAX186/MAX188 generate

their own conversion clock internally. This frees the

microprocessor from the burden of running the SAR con-

version clock, and allows the conversion results to be

read back at the processor’s convenience, at any clock

rate from zero to typically 10MHz. SSTRB goes low at the

start of the conversion and then goes high when the con-

version is complete. SSTRB will be low for a maximum of

10µs, during which time SCLK should remain low for best

noise performance. An internal register stores data when

the conversion is in progress. SCLK clocks the data out

at this register at any time after the conversion is com-

plete. After SSTRB goes high, the next falling clock edge

will produce the MSB of the conversion at DOUT, fol-

lowed by the remaining bits in MSB-first format (see

Figure 9). CS does not need to be held low once a con-

version is started. Pulling CS high prevents data from

being clocked into the MAX186/MAX188 and three-

states DOUT, but it does not adversely effect an internal

clock-mode conversion already in progress. When inter-

nal clock mode is selected, SSTRB does not go into a

high-impedance state when CS goes high.

Figure 10 shows the SSTRB timing in internal clock

mode. In internal clock mode, data can be shifted in and

out of the MAX186/MAX188 at clock rates exceeding

4.0MHz, provided that the minimum acquisition time, t

is kept above 1.5µs.

MAX186/MAX188

Low-Power, 8-Channel,

Serial 12-Bit ADCs

______________________________________________________________________________________ 13

• • •

SDV

SSTRB

PD0 CLOCKED IN

STR

SSTRB

SCLK

SSTRB

• • •

• • • • •

SSTRB

SCLK

DIN

DOUT

14 8

START

SEL2 SEL1 SEL0

UNI/

DIP

SCL/

DIFF

PD1 PD0

B11

MSB

B10 B9 B2 B1

B0

LSB

ACQUISITION



1.5µs (CLK = 2MHz)

IDLE

FILLED WITH 

ZEROS

IDLE

CONVERSION

10µs MAX

A/D STATE

2 3 5 6 7 9 10 11 19 21 22 23

CONV

Figure 8. External Clock Mode SSTRB Detailed Timing

Figure 9. Internal Clock Mode Timing

MAX186/MAX188

Data Framing

The falling edge of CS does not start a conversion on the

MAX186/MAX188. The first logic high clocked into DIN is

interpreted as a start bit and defines the first bit of the

control byte. A conversion starts on the falling edge of

SCLK, after the eighth bit of the control byte (the PD0 bit)

is clocked into DIN. The start bit is defined as:

The first high bit clocked into DIN with CS low any-

time the converter is idle, e.g. after V

is applied.

The first high bit clocked into DIN after bit 5 of a

conversion in progress is clocked onto the DOUT pin.

If a falling edge on CS forces a start bit before bit 5

(B5) becomes available, then the current conversion

will be terminated and a new one started. Thus, the

fastest the MAX186/MAX188 can run is 15 clocks per

conversion. Figure 11a shows the serial-interface timing

necessary to perform a conversion every 15 SCLK

cycles in external clock mode. If CS is low and SCLK is

continuous, guarantee a start bit by first clocking in 16

zeros.

Most microcontrollers require that conversions occur in

multiples of 8 SCLK clocks; 16 clocks per conversion

will typically be the fastest that a microcontroller can

drive the MAX186/MAX188. Figure 11b shows the

serial-interface timing necessary to perform a conver-

sion every 16 SCLK cycles in external clock mode.

__________ Applications Information

Power-On Reset

When power is first applied and if SHDN is not pulled

low, internal power-on reset circuitry will activate the

MAX186/MAX188 in internal clock mode, ready to con-

vert with SSTRB = high. After the power supplies have

been stabilized, the internal reset time is 100µs and no

conversions should be performed during this phase.

SSTRB is high on power-up and, if CS is low, the first

logical 1 on DIN will be interpreted as a start bit. Until a

conversion takes place, DOUT will shift out zeros.

Reference-Buffer Compensation

In addition to its shutdown function, the SHDN pin also

selects internal or external compensation. The compen-

sation affects both power-up time and maximum conver-

sion speed. Compensated or not, the minimum clock

rate is 100kHz due to droop on the sample-and-hold.

To select external compensation, float SHDN. See the

Typical Operating Circuit

, which uses a 4.7µF capacitor at

VREF. A value of 4.7µF or greater ensures stability and

allows operation of the converter at the full clock speed of

2MHz. External compensation increases power-up time (see

the

Choosing Power-Down Mode

section, and Table 5).

Internal compensation requires no external capacitor at

VREF, and is selected by pulling SHDN high. Internal com-

pensation allows for shortest power-up times, but is only

available using an external clock and reduces the maxi-

mum clock rate to 400kHz.

Low-Power, 8-Channel,

Serial 12-Bit ADCs

14 ______________________________________________________________________________________

PD0 CLOCK IN

SSTRB

CSH

CONV

SCK

SSTRB • • •

SCLK • • •

CSS

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

CS • • •

Figure 10. Internal Clock Mode SSTRB Detailed Timing

Power-Down

Choosing Power-Down Mode

You can save power by placing the converter in a

low-current shutdown state between conversions.

Select full power-down or fast power-down mode via

bits 7 and 8 of the DIN control byte with SHDN high or

floating (see Tables 2 and 6). Pull SHDN low at any time

to shut down the converter completely. SHDN overrides

bits 7 and 8 of DIN word (see Table 7).

Full power-down mode turns off all chip functions that draw

quiescent current, reducing I

and I

typically to 2µA.

Fast power-down mode turns off all circuitry except the

bandgap reference. With the fast power-down mode, the

supply current is 30µA. Power-up time can be shortened

to 5µs in internal compensation mode.

In both software shutdown modes, the serial interface

remains operational, however, the ADC will not convert.

Table 5 illustrates how the choice of reference-buffer

compensation and power-down mode affects both

power-up delay and maximum sample rate.

In external compensation mode, the power-up time is

20ms with a 4.7µF compensation capacitor (200ms with

a 33µF capacitor) when the capacitor is fully discharged.

In fast power-down, you can eliminate start-up time by

using low-leakage capacitors that will not discharge

more than 1/2LSB while shut down. In shutdown, the

capacitor has to supply the current into the reference

(1.5µA typ) and the transient currents at power-up.

Figures 12a and 12b illustrate the various power-down

sequences in both external and internal clock modes.

Software Power-Down

Software power-down is activated using bits PD1 and

PD0 of the control byte. As shown in Table 6, PD1 and

PD0 also specify the clock mode. When software shut-

down is asserted, the ADC will continue to operate in

the last specified clock mode until the conversion is

complete. Then the ADC powers down into a low quies-

cent-current state. In internal clock mode, the interface

remains active and conversion results may be clocked

out while the MAX186/MAX188 have already entered a

software power-down.

The first logical 1 on DIN will be interpreted as a start

bit, and powers up the MAX186/MAX188. Following the

start bit, the data input word or control byte also deter-

mines clock and power-down modes. For example, if

the DIN word contains PD1 = 1, then the chip will

remain powered up. If PD1 = 0, a power-down will

resume after one conversion.

MAX186/MAX188

Low-Power, 8-Channel,

Serial 12-Bit ADCs

______________________________________________________________________________________ 15

SCLK

DIN

DOUT

S CONTROL BYTE 0

CONTROL BYTE 1S

CONVERSION RESULT 0

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 1

SSTRB

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONTROL BYTE 2S

8181

SCLK

DIN

DOUT

S CONTROL BYTE 0

CONTROL BYTE 1S

CONVERSION RESULT 0

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B11 B10 B9 B8

CONVERSION RESULT 1

• • •

Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing

Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

MAX188ACWP+

Mfr. #:

Buy MAX188ACWP+

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 12-Bit 8Ch 133ksps 5.25V Precision ADC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX188ACWP+

MAX188ACWP+

Products related to this Datasheet