MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
16 ______________________________________________________________________________________
Reference Reference- VREF Power- Power-Up Maximum
Buffer Buffer Capacitor Down Delay Sampling
Compensation (µF) Mode (sec) Rate (ksps)
Mode
Enabled Internal Fast 26
Enabled Internal Full 300µ 26
Enabled External 4.7 Fast See Figure 14c 133
Enabled External 4.7 Full See Figure 14c 133
Disabled Fast 133
Disabled Full 133
Table 5. Typical Power-Up Delay Times
PD1 PD0 Device Mode
1 1 External Clock Mode
1 0 Internal Clock Mode
0 1 Fast Power-Down Mode
0 0 Full Power-Down Mode
Device Reference-Buffer
State Mode Compensation
1 Enabled Internal Compensation
Floating Enabled External Compensation
0 Full Power-Down N/A
Table 6. Software Shutdown and Clock Mode
Table 7. Hard-Wired Shutdown and
Compensation Mode
POWERED UP
FULL
POWER
DOWN
POWERED
UP
POWERED UP
DATA VALID
(12 DATA BITS)
DATA VALID
(12 DATA BITS)
DATA INVALID
VALID
EXTERNAL
EXTERNAL
INTERNAL
SX
XXXX
11 S 01
XXXXX XXXXX
S11
FAST
POWER-DOWN
MODE
DOUT
DIN
CLOCK
MODE
SHDN
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
SETS FAST
POWER-DOWN 
MODE
Figure 12a. Timing Diagram Power-Down Modes, External Clock
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________ 17
FULL
POWER-DOWN
POWERED
UP
POWERED UP
DATA VALID
DATA VALID
INTERNAL CLOCK MODE
SX
XXXX
10 S 00
XXXXX 
S
MODE
DOUT
DIN
CLOCK
MODE
SETS INTERNAL
CLOCK MODE
SETS FULL
POWER-DOWN
CONVERSION
CONVERSION
SSTRB
100
DIN
REFADJ
VREF
2.5V
0V
4V
0V
101 1 11100 101
FULLPD FASTPD NOPD FULLPD FASTPD
2ms WAIT
COMPLETE CONVERSION SEQUENCE
t
BUFFEN
15µs
τ = RC = 20k x C
REFADJ
(ZEROS)
CH1 CH7
(ZEROS)
Hardware Power-Down
The SHDN pin places the converter into the full
power-down mode. Unlike with the software shut-down
modes, conversion is not completed. It stops coinci-
dentally with SHDN being brought low. There is no
power-up delay if an external reference is used and is
not shut down. The SHDN pin also selects internal or
external reference compensation (see Table 7).
Power-Down Sequencing
The MAX186/MAX188 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. The following discussion illus-
trates the various power-down sequences.
Lowest Power at up to 500
Conversions/Channel/Second
The following examples illustrate two different power-down
sequences. Other combinations of clock rates, compen-
sation modes, and power-down modes may give lowest
power consumption in other applications.
Figure 14a depicts the MAX186 power consumption for
one or eight channel conversions utilizing full
power-down mode and internal reference compensation.
A 0.01µF bypass capacitor at REFADJ forms an RC filter
with the internal 20k reference resistor with a 0.2ms
time constant. To achieve full 12-bit accuracy, 10 time
constants or 2ms are required after power-up. Waiting
2ms in FASTPD mode instead of full power-up will reduce
the power consumption by a factor of 10 or more. This is
achieved by using the sequence shown in Figure 13.
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
Figure 13. MAX186 FULLPD/FASTPD Power-Up Sequence
MAX186/MAX188
Lowest Power at Higher Throughputs
Figure 14b shows the power consumption with
external-reference compensation in fast power-down,
with one and eight channels converted. The external
4.7µF compensation requires a 50µs wait after power-up,
accomplished by 75 idle clocks after a dummy conver-
sion. This circuit combines fast multi-channel conversion
with lowest power consumption possible. Full
power-down mode may provide increased power sav-
ings in applications where the MAX186/MAX188 are
inactive for long periods of time, but where intermittent
bursts of high-speed conversions are required.
External and Internal References
The MAX186 can be used with an internal or external
reference, whereas an external reference is required for
the MAX188. Diode D1 shown in the
Typical Operating
Circuit
ensures correct start-up. Any standard signal
diode can be used. For both parts, an external refer-
ence can either be connected directly at the VREF ter-
minal or at the REFADJ pin.
An internal buffer is designed to provide 4.096V at
VREF for both the MAX186 and MAX188. The
MAX186’s internally trimmed 2.46V reference is
buffered with a gain of 1.678. The MAX188's buffer is
trimmed with a buffer gain of 1.638 to scale an external
2.5V reference at REFADJ to 4.096V at VREF.
MAX186 Internal Reference
The full-scale range of the MAX186 with internal reference
is 4.096V with unipolar inputs, and ±2.048V with bipolar
inputs. The internal reference voltage is adjustable to
±1.5% with the Reference-Adjust Circuit of Figure 17.
External Reference
With both the MAX186 and MAX188, an external refer-
ence can be placed at either the input (REFADJ) or the
output (VREF) of the internal buffer amplifier. The
REFADJ input impedance is typically 20k for the
MAX186 and higher than 100k for the MAX188, where
the internal reference is omitted. At VREF, the input
impedance is a minimum of 12k for DC currents.
During conversion, an external reference at VREF must
be able to deliver up to 350µA DC load current and have
an output impedance of 10 or less. If the reference has
higher output impedance or is noisy, bypass it close to
the VREF pin with a 4.7µF capacitor.
Low-Power, 8-Channel,
Serial 12-Bit ADCs
18 ______________________________________________________________________________________
1000
1
0 100 300 500
MAX186
FULL POWER-DOWN
10
100
MAX186-14A
CONVERSIONS PER CHANNEL PER SECOND
200 400
2ms FASTPD WAIT
400kHz EXTERNAL CLOCK
INTERNAL COMPENSATION
50 150 250 350 450
8 CHANNELS
1 CHANNEL
AVG. SUPPLY CURRENT (µA)
10,000
10
0
MAX186/MAX188
FAST POWER-DOWN
100
1000
CONVERSIONS PER CHANNEL PER SECOND
2k
8 CHANNELS
1 CHANNEL
4k 6k 8k 10k 12k 14k 16k 18k
2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
50µs WAIT
AVG. SUPPLY CURRENT (µA)
Figure 14a. MAX186 Supply Current vs. Sample Rate/Second,
FULLPD, 400kHz Clock
Figure 14b. MAX186/MAX188 Supply Current vs. Sample
Rate/Second, FASTPD, 2MHz Clock
3.0
2.5
2.0
1.5
1.0
0.5
0
0.0001 0.001 0.01 0.1 1 10
TIME IN SHUTDOWN (sec)
POWER-UP DELAY (ms)
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown

MAX188ACWP+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 8Ch 133ksps 5.25V Precision ADC
Lifecycle:
New from this manufacturer.
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