6.42
3
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
SEPTEMBER 29, 2011
Pin Names
Left Port Right Port Description
CS
L
CS
R
Chip Select (Input)
WE
L
WE
R
Read/Write Enable (Input)
OE
L
OE
R
Output Enable (Input)
A
0R
- A
13R
(1)
Address (Input)
MSEL
(2)
Mode Select (Input)
I/O
0L
- I/O
15L
I/O
0R
- I/O
15R
Address/Data (Input/Output)
ADV
L
ADV
R
(3)
Address Latch Enable (Input)
UB
L
UB
R
Upper Byte Enable (Input)
LB
L
LB
R
Lower Byte Enable (Input)
INT
L
INT
R
Interrupt Flag (Output)
BUSY
L
BUSY
R
Busy Flag (Output)
SFEN
Special Function Enable (Input)
IRR
0
- IRR
1
(4)
Input Read Register (Inputs)
ODR
0
- ODR
4
Output Drive Register (Outputs)
VDD Core Power Supply (Input)
VSS Ground (Input)
VDDIO
L
Left Port Power Supply (Input)
VDDIO
R
Right Port Power Supply (Input)
DNU Do Not Use
7145 tbl 01
Truth Table I: ADM Interface Read/Write Control
Inputs Outputs
Mode
ADVCSWEOEUB LB
I/O
0 -
I/O
15
X H X X X X High-Z Deselected/Power Down
X X X H X X High-Z Output Disable
X X X X H H High-Z Upper and Lower Bytes Deselected
PulseLHLLLDATA
OUT
(I/O
0
- I/O
15
) Read Upper and Lower Bytes
Pulse L H L H L
DATA
OUT
(I/O
0
- I/O
7
)
High-Z (I/O
8
- I/O
15
) Read Lower Byte Only
Pulse L H L L H
High-Z (I/O
0
- I/O
7
)
DATA
OUT
(I/O
8
- I/O
15
) Read Upper Byte Only
Pulse L L X L L DATA
IN
(I/O
0
- I/O
15
) Write Upper and Lower Bytes
Pulse L L X H L
DATA
IN
(I/O
0
- I/O
7
)
High-Z (I/O
8
- I/O
15
) Write Lower Byte Only
Pulse L L X L H
High-Z (I/O
0
- I/O
7
)
DATA
IN
(I/O
8
- I/O
15
) Write Upper Byte Only
7145 tbl 02a
1. A13 - A0 for IDT70P265; A12 - A0 for IDT70P255; A11 - A0 for IDT70P245.
2. MSEL = 0 for Standard SRAM operation, MSEL = 1 for Address/Data Mux
(ADM) operation.
3. ADV
R is only used when the right port is in ADM mode.
4. IRR
0 is DNU and IRR1 is A13R for 70P265.
NOTES:
