6.42
13
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
SEPTEMBER 29, 2011
tAW
Valid AddressAddress
CS
OE
WE
UB, LB
tWC
tBW
Valid DataData
tSA tHA
tHZWE
tWRL
tLZWE
tSD
tHD
Standard Port Write Cycle (Right Port Access, WE Controlled)
tAW
Valid AddressAddress
CS
OE
WE
UB, LB
tWC
tBW
Valid DataData
tSA
tHA
tHZWE
tWRL
tS D
tHD
tLZCStSCS
Standard Port Write Cycle (Right Port Access, CS Controlled)
6.42
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
14 SEPTEMBER 29, 2011
Address MatchAddress
CS
R
CS
L
BUSY
L
tPS
tBLC tBH C
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(1)
NOTES:
1. VDD = 1.8V.
2. Add 2 ns to this parameter if V
DD and VDDIOR are <1.8V, and VDDIOL is >2.5V at temperature <0
O
C.
Symbol Parameter
70P265/255/245
Unit
65 ns 90 ns
Min. Max. Min. Max..
Arbitration Timing
t
BLA
BUSY Low from Address Match
____
30
____
50 ns
t
BHA
BUSY High from Address Match
____
30
____
50 ns
t
BLC
BUSY Low from CS Low
____
30
____
50 ns
t
BHC
BUSY High from CS High
____
30
____
50 ns
t
PS
(2)
Port Set-up Priority 5
____
5
____
ns
t
BDD
BUSY High to Data Valid
____
30
____
50
ns
t
WDD
Write Pulse to Data Delay
____
55
____
85 ns
t
DDD
Write Data Valid to Read Data Valid
____
45
____
70 ns
7145 tbl 14
Arbitration Timing
6.42
15
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
SEPTEMBER 29, 2011
Left Address Valid First
ADV
L
Address
L
(Internal)
Address
R
BUSY
R
I/O
L
[15:0]
tAVDH
A
0
tPS
tBLA tBHA
A
0
A
1
I/O
L
[15:0]
ADV
L
Address
L
(Internal)
Address
R
BUSY
L
A
0
Data A
1
tAVDH
tPS
tBHA
tBLA
A
0
A
0
A
1
tAVDH
Right Address Valid First
A
0
Arbitration Timing
(Address Controlled with Left ADM and Right STD Configuration)

70P245L90BYGI8

Mfr. #:
Manufacturer:
Description:
IC SRAM 64K PARALLEL 100CABGA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union