Once the address has been programmed, the data
stored in that address is transferred to the TFR[7:0] bits
in the ROM Table Data Readback register (Table 13).
The ROM data at the specified address can then be
read from the TFR[7:0] bits and stored in the micro-
processor’s local memory.
Interpolating Tracking Filter Coefficients
The TFS[7:0] and TFP[5:0] bits must be reprogrammed
for each channel frequency to optimize performance.
The optimal settings for each channel can be calculat-
ed from the ROM table data using the equations below:
VHF filter:
UHF filter:
:
where:
f
RF
= operating frequency in megahertz.
TFS = decimal value of the optimal TFS[7:0] setting
(Table 9) for the given operating frequency.
TFP = decimal value of the optimal TFP[5:0] setting
(Table 10) for the given operating frequency.
VS0, VS1, VP0, VP1, US0, US1, UP0, and UP1 = the
decimal values of the ROM table coefficients (Table
16).
IF Overload Detector
The MAX3541 includes a broadband IF overload detec-
tor, which provides an indication of the total power pre-
sent at the RF input. The overload-detector output voltage
is compared to a reference voltage, and the difference is
amplified. This error signal drives an open-collector tran-
sistor whose collector is connected to the IFOVLD pin,
causing the IFOVLD pin to sink current. The nominal full-
scale current sunk by the IFOVLD pin is 300μA. The
IFOVLD pin requires a 10kΩ pullup resistor to V
CC
.
The IF overload detector is calibrated at the factory to
attack at 0.7V
P-P
at the IFOUT1. Upon power-up, the
baseband processor must read OD[2:0] from the ROM
table and store it in the IFVOLD register.
Closed-Loop RF Gain Control
Closed-loop RF gain control can be implemented by
connecting the IFOVLD output to the RFAGC input.
Using a 10kΩ pullup resistor on the IFOVLD pin as
shown in the
Typical Application Circuit
results in a
nominal control voltage range of 0.5V to 3V.
VCO and VCO Divider Selection
The MAX3541 frequency synthesizer includes three
VCOs and eight VCO sub-bands to guarantee a
2200MHz to 4400MHz VCO frequency range. The fre-
quency synthesizer also features an additional VCO fre-
quency divider that must be programmed to either 4, 8,
16, or 32 by the VDIV[1:0] bits in the VCO register based
on the channel being received.
To ensure PLL lock, the proper VCO and VCO sub-band
for the channel being received must be chosen by itera-
tively selecting a VCO and VCO sub-band, then reading
the LD[2:0] bits to determine if the PLL is locked. Any
reading from 001 to 110 indicates the PLL is locked. If
LD[2:0] reads 000, the PLL is unlocked and the selected
VCO is at the bottom of its tuning range; a lower VCO
sub-band must be selected. If LD[2:0] reads 111, the PLL
is unlocked and the selected VCO is at the top of its tun-
ing range; a higher VCO sub-band must be selected. The
VCO and VCO sub-band settings should be progressive-
ly increased or decreased until the LD[2:0] reading falls in
the 001 to 110 range.
Due to overlap between VCO sub-band frequencies, it is
possible that multiple VCO settings can be used to tune
to the same channel frequency. System performance at
a given channel should be similar between the various
possible VCO settings, so it is sufficient to select the first
VCO and VCO sub-band that provides lock.
Layout Considerations
The MAX3541 EV kit can serve as a guide for PCB lay-
out. Keep RF signal lines as short as possible to mini-
mize losses and radiation. Use controlled impedance on
all high-frequency traces. The exposed paddle must be
soldered evenly to the board’s ground plane for proper
operation. Use abundant vias beneath the exposed pad-
dle for maximum heat dissipation. Use abundant ground
vias between RF traces to minimize undesired coupling.
To minimize coupling between different sections of the
IC, the ideal power-supply layout is a star configuration,
which has a large decoupling capacitor at the central
V
CC
node. The V
CC
traces branch out from this node,
with each trace going to separate V
CC
pins of the
MAX3541. Each V
CC
pin must have a bypass capacitor
with a low impedance to ground at the frequency of
interest. Do not share ground vias among multiple con-
nections to the PCB ground plane.
