8
LT3781
3781f
UU
U
PI FU CTIO S
The error amplifier is typically configured using a feedback
RC network to realize an integrator circuit. This circuit
creates the dominant pole for the converter regulation
feedback loop. Integrator characteristics are dominated
by the value of the capacitor connected from the V
C
pin to
the V
FB
pin and the feedback resistor connected to the V
FB
pin. Specific integrator characteristics can be configured
to optimize transient response.
The error amplifier can also be configured as a
transimpedance amplifier for use in secondary-side con-
troller applications. (See the Applications Information
section for configuration and compensation details)
SENSE (Pin 11): Current Sense Amplifier (CSA)
Noninverting Input. Current is monitored via a ground
referenced current sense resistor, typically in series with
the source of the bottom side switch FET. Internal current
limit circuitry provides for a maximum peak value of
150mV across the sense resistor during normal opera-
tion.
SG (Pin 12): Synchronous Switch Output Driver. This pin
can be connected directly to gate of synchronous switch
if small FETs are used (C
GATE
< 5000pF), however, the use
of a gate drive buffer is recommended for peak efficien-
cies.
The SG pin output is synchronized and out-of-phase with
the BG output. The control timing of the SG output cause
it to “lead” the primary switch path during turn-on by
150nS.
V
CC
(Pin 13): IC
Local Power Supply Input. Bypass with at
a capacitor at least 10 times greater than C5V
REF
. LT3781
incorporates undervoltage lockout that disables switching
functions if V
CC
is below 8.4V. The LT3781 supports
operational V
CC
power supply voltages from 9V to 18V
(20V absolute maximum). An 18V clamp on the V
CC
pin is
enabled during shutdown mode, preventing a trickle start
circuit from pulling that pin above maximum operational
levels during IC shutdown.
PWRGND (Pin 14): Output Driver Ground Reference.
Connect through low impedance trace to V
IN
decoupling
capacitor.
BG (Pin 15): Bottom Side Primary Switch/Forward Switch
Output Driver. This pin can be connected directly to
gate(s) of primary bottom side and forward switches if
small FETs are used (C
GATE
total < 5000pF), however, the
use of a gate drive buffer is recommended for peak
efficiencies.
The BG output is enabled at the start of each oscillator
cycle in phase with the TG pin but is timed to “lag” the TG
output during turn-on and “lead” the TG output during
turn-off. These delays force the concentration of transi-
tional losses onto the bottom side primary switch.
An adaptive blanking circuit disables the current sense
function (via the SENSE pin) while the BG pin is below 5V.
BSTREF (Pin 18): V
BST
Supply Reference. Typically con-
nects to source of topside external power FET switch.
TG (Pin 19): Topside (Boosted) Primary Output Driver.
This pin can be connected directly to gate of primary
topside switch if small FETs are used (C
GATE
< 5000pF),
however, the use of a gate drive buffer is recommended for
peak efficiencies.
V
BST
(Pin 20): Topside Primary Driver Bootstrapped Sup-
ply. This “boosted” supply rail is referenced to the BSTREF
pin.
Supply voltage is maintained by a bootstrap capacitor tied
from the V
BST
pin to the boosted supply reference (BSTREF)
pin. The charge on the capacitor is refreshed each switch
cycle through a Schottky diode connected from the V
CC
supply (cathode) to the V
BST
pin (anode). The bootstrap
capacitor (C
BOOST
) must be at least 100 times greater than
the total load capacitance on the TG pin. A capacitor in the
range of 0.1µF to 1.0µF is generally adequate for most
applications. The bootstrap diode must have a reverse
breakdown voltage greater than the converter V
IN
. The
LT3781 supports operational V
BST
supply voltages up to
90V (absolute maximum) referenced to ground.
Undervoltage Lockout disables the topside switch until
V
BST
– BSTREF > 7.0V for start-up protection of the
topside switch.
