Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. E
01/29/08
IS62WV5128ALL, IS62WV5128BLL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
55 ns 70 ns
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 55 — 70 — ns
tSCS1 CS1 to Write End 45 — 60 — ns
tAW Address Setup Time to Write End 45 — 60 — ns
tHA Address Hold from Write End 0 — 0 — ns
tSA Address Setup Time 0 — 0 — ns
tPWE WE Pulse Width 40 — 50 — ns
tSD Data Setup to Write End 25 — 30 — ns
tHD Data Hold from Write End 0 — 0 — ns
tHZWE
(3)
WE LOW to High-Z Output — 20 — 20 ns
tLZWE
(3)
WE HIGH to Low-Z Output 5 — 5 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
V
DD-0.2V/VDD-0.3V and output loading specified in Figure 1.
2.
The internal write time is defined by the overlap of CS1 LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1 Controlled, OE = HIGH or LOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
WE
DOUT
DIN
