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ADM4856AR-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
5 V, Slew Rate Limited, Half-Duplex and
Full Duplex RS-485/RS-422 Transceivers
Data Sheet
ADM4850 to ADM4857
Rev. F Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Electronics industries alliance (EIA) RS-485/RS-422 compliant
Data rate options
ADM4850/ADM4854: 115 kbps
ADM4851/ADM4855: 500 kbps
ADM4852/ADM4856: 2.5 Mbps
ADM4853/ADM4857: 10 Mbps
Half-duplex and full duplex options
Reduced slew rates for low electromagnetic interference (EMI)
True fail-safe receiver inputs
5 µA (maximum) supply current in shutdown mode
Up to 256 transceivers on one bus
Outputs high-Z when disabled or powered off
−7 V to +12 V bus common-mode range
Thermal shutdown and short-circuit protection
Pin-compatible with the MAX308x
Specified over the −40°C to +85°C temperature range
Available in 8-lead SOIC, 8-lead LFCSP, and 8-lead MSOP
Qualified for automotive applications
APPLICATIONS
Low power RS-485 applications
EMI sensitive systems
DTE to DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
GENERAL DESCRIPTION
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 are differential line transceivers
suitable for high speed, half-duplex and full duplex data
communication on multipoint bus transmission lines. They
are designed for balanced data transmission and comply with
EIA Standards RS-485 and RS-422. The ADM4850/ADM4851/
ADM4852/ADM4853 are half-duplex transceivers that share
differential lines and have separate enable inputs for the driver
and receiver. The full duplex ADM4854/ADM4855/ADM4856/
ADM4857 transceivers have dedicated differential line driver
outputs and receiver inputs.
The devices have a 1/8-unit load receiver input impedance,
which allows up to 256 transceivers on one bus. Because only one
driver must be enabled at any time, the output of a disabled or
powered down driver is three-stated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which ensures a
logic high output level when the inputs are open or shorted.
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. ADM4850/ADM4851/ADM4852/ADM4853 Functional Block Diagram
Figure 2. ADM4854/ADM4855/ADM4856/ADM4857 Functional Block Diagram
This guarantees that the receiver outputs are in a known state
before communication begins and when communication ends.
The driver outputs are slew rate limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or by
output shorting is prevented with a thermal shutdown circuit.
The devices are fully specified over the commercial and industrial
temperature ranges and are available in 8-lead SOIC (ADM4850
through ADM4857), 8-lead LFCSP (ADM4850/ADM4852/
ADM4853), and 8-lead MSOP (ADM4850 only) packages.
Table 1. Selection Table
Device No. Half-Duplex/Full Duplex Data Rate
ADM4850 Half 115 kbps
ADM4851 Half 500 kbps
ADM4852 Half 2.5 Mbps
ADM4853 Half 10 Mbps
ADM4854 Full 115 kbps
ADM4855 Full 500 kbps
ADM4856 Full 2.5 Mbps
ADM4857 Full 10 Mbps
04931-001
RO
RE
R
DE
DI
D
A
B
GND
V
CC
ADM4850/ADM4851/
ADM4852/ADM4853
04931-028
RO
R
A
B
DI
D
Z
Y
GND
V
CC
ADM4854/ADM4855/
ADM4856/ADM4857
ADM4850 to ADM4857 Data Sheet
Rev. F | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
ADM4850/ADM4854 Timing Specifications ........................... 4
ADM4851/ADM4855 Timing Specifications ........................... 4
ADM4852/ADM4856 Timing Specifications ........................... 5
ADM4853/ADM4857 Timing Specifications ........................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Test Circuits ..................................................................................... 11
Switching Characteristics .............................................................. 12
Theory of Operation ...................................................................... 13
Slew Rate Control ....................................................................... 13
Receiver Input Filtering ............................................................. 13
Half-Duplex/Full Duplex Operation ....................................... 13
High Receiver Input Impedance .............................................. 14
Three-State Bus Connection ..................................................... 14
Shutdown Mode ......................................................................... 14
Fail-Safe Operation .................................................................... 14
Current Limit and Thermal Shutdown ................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
Automotive Product ................................................................... 16
REVISION HISTORY
5/16—Rev. E to Rev. F
C
hanges to Figure 1 .......................................................................... 1
Reformatted and Changes to Pin Configuration and Function
Descriptions Section ........................................................................ 7
Added Figure 6, Renumbered Sequentially .................................. 8
2/1
6—Rev. D to Rev. E
Changes to Figure 1 and General Description Section ...............
1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 and Table 4 ....................................................... 4
Changes to Table 5 and Table 6 ....................................................... 5
Changes to Figure 3, Figure 4, and Table 8 Caption .................... 7
Added Table 9; Renumbered Sequentially .................................... 7
Changes to Figure 5 and Table 10 Caption ................................... 8
Changes to Figure 6 Caption ........................................................... 9
Changes to Figure 14 Caption and Figure 15 Caption .............. 10
Changes to Figure 21 Caption and Figure 23 Caption .............. 11
Changed Circuit Description Section to Theory of Operation
Section .............................................................................................. 13
Changes to Figure 28 ...................................................................... 13
Changes to the Three-State Bus Connection Section and the
Shutdown Mode Section ................................................................ 14
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 16
1/12—Rev. C to Rev. D
Change to Features Section .............................................................. 1
Changes to Ordering Guide .......................................................... 15
Added Automotive Products Section .......................................... 15
1/11—Rev. B to Rev. C
Change to Table 8, Pin 3 Description ............................................. 7
Changes to Figure 29...................................................................... 12
Changes to Ordering Guide .......................................................... 15
7/09—Rev. A to Rev. B
Added MSOP Package ....................................................... Universal
Changes to Table 2 ............................................................................. 3
Changes to Table 7 ............................................................................. 6
Inserted Figure 4; Renumbered Sequentially ................................ 7
Moved Typical Performance Characteristics Section ................... 8
Changes to Figure 24 and Figure 27 ............................................ 11
Changes to Figure 29...................................................................... 12
Change to Shutdown Mode Section............................................. 13
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
4/0
9—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 15
10/04—R
evision 0: Initial Version
Data Sheet ADM4850 to ADM4857
Rev. F | Page 3 of 16
SPECIFICATIONS
V
CC
= 5 V ± 5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Voltage V
OD
V
CC
V R = ∞, see Figure 19
1
2.0 5 V R = 50 Ω (RS-422), see Figure 19
1.5 5 V R = 27 Ω (RS-485), see Figure 19
Differential Output Voltage over Common-
Mode Range
|V
OD3
| 1.5 5 V V
TST
= −7 V to +12 V, see Figure 20
Δ|V
OD
| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 19
Common-Mode Output Voltage V
OC
3 V R = 27 Ω or 50 Ω, see Figure 19
Δ|V
OC
| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 19
Output Short-Circuit Current −7 V < V
OUT
< +12 V
V
OUT
= High −200 +200 mA
V
OUT
= Low −200 +200 mA
DRIVER INPUT LOGIC
CMOS Input Logic Threshold
Low 0.8 V
High 2.0 V
CMOS Logic Input Current (DI) ±1 µA
DE Input Resistance to GND 220 kΩ
RECEIVER
Differential Input Threshold Voltage V
TH
−200 −125 −30 mV −7 V < V
OC
< +12 V
Input Hysteresis 20 mV −7 V < V
OC
< +12 V
Input Resistance (A, B) 96 150 kΩ −7 V < V
OC
< +12 V
Input Current (A, B) 0.125 mA V
IN
= 12 V
−0.1 mA V
IN
= −7 V
CMOS Logic Input Current (
RE
) ±1 µA
CMOS Output Voltage
Low 0.4 V I
OUT
= 4 mA
High 4.0 V I
OUT
= −4 mA
Output Short-Circuit Current 7 85 mA V
OUT
= GND or V
CC
Three-State Output Leakage Current ±2 µA 0.4 V ≤ V
OUT
≤ 2.4 V
POWER SUPPLY CURRENT
115 kbps Options (ADM4850/ADM4854) 5 µA DE = 0 V,
RE
= V
CC
(shutdown)
36 60 µA DE = 0 V,
RE
= 0 V
100 160 µA DE = V
CC
500 kbps Options (ADM4855) 5 µA DE = 0 V,
RE
= V
CC
(shutdown)
80 120 µA DE = 0 V,
RE
= 0 V
120 200 µA DE = V
CC
2.5 Mbps Options (ADM4852/ADM4856) 5 µA DE = 0 V,
RE
= V
CC
(shutdown)
250 400 µA DE = 0 V,
RE
= 0 V
320 500 µA DE = V
CC
10 Mbps Options (ADM4853/ADM4857) 5 µA DE = 0 V,
RE
= V
CC
(shutdown)
250 400 µA DE = 0 V,
RE
= 0 V
320 500 µA DE = V
CC
1
Guaranteed by design.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ADM4856AR-REEL

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Manufacturer:
Analog Devices Inc.
Description:
IC TXRX RS485/422 2.5MBPS 8SOIC
Lifecycle:
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