Data Sheet ADM4850 to ADM4857
Rev. F | Page 13 of 16
THEORY OF OPERATION
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 are high speed RS-485/RS-422
transceivers offering enhanced performance over industry-
standard devices. All devices in the family contain one driver
and one receiver but offer a choice of performance options. The
devices feature true fail-safe operation, which guarantees a logic
high receiver output when the receiver inputs are open circuit
or short-circuit, or when they are connected to a terminated
transmission line with all drivers disabled (see the Fail-Safe
Operation section).
SLEW RATE CONTROL
The ADM4850 and ADM4854 feature a controlled slew rate
driver that minimizes EMI and reduces reflections caused by
incorrectly terminated cables, allowing error free data transmission
rates up to 115 kbps. The ADM4851 and ADM4855 offer a higher
limit on driver output slew rate, allowing data transmission
rates up to 500 kbps. The driver slew rates of the ADM4852/
ADM4856 and the ADM4853/ADM4857 are not limited,
offering data transmission rates up to 2.5 Mbps and 10 Mbps,
respectively.
RECEIVER INPUT FILTERING
The receivers of all the devices incorporate input hysteresis. In
addition, the receivers of the 115 kbps ADM4850 and ADM4854
and the 500 kbps ADM4851 and ADM4855 incorporate input
filtering, which enhances noise immunity with differential
signals that have very slow rise and fall times. However, it
causes the propagation delay to increase by 20%.
HALF-DUPLEX/FULL DUPLEX OPERATION
Half-duplex operation implies that the transceiver can transmit and
receive, but it can do only one of these at any given time. However,
with full duplex operation, the transceiver can transmit and
receive simultaneously. The ADM4850/ADM4851/ADM4852/
ADM4853 are half-duplex devices in which the driver and the
receiver share differential bus terminals. The ADM4854/
ADM4855/ADM4856/ADM4857 are full duplex devices that
have dedicated driver output and receiver input pins. Figure 29
and Figure 30 show typical half-duplex and full duplex topologies.
F
igure 29. Typical Half-Duplex RS-485 Network Topology
F
igure 30. Typical Full Duplex Point-to-Point RS-485 Network Topology
04931-026
RO
RE
DE
DI
D
R
A
B
MAXIMUM NUMBER OF TRANSCEIVERS ON BUS: 256
RO
RE
DE
DI
D
R
A
B
R
D
RO RE DE DI
A B
R
D
RO RE DE DI
A B
ADM4850/
ADM4852/ADM4853
ADM4850/
ADM4852/ADM4853
ADM4850
ADM4852/ADM4853
ADM4850/
ADM4852/ADM4853
NOTES
1. THE ADM4851 IS A HALF-DUPLEX RS-485 TRANSCEIVER, BUT IT DOES NOT HAVE THE DRIVER ENABLE (DE) AND THE RECEIVER ENABLE (RE) PINS.
04931-027
GND
RO
DI
D
R
A
B
RO
DI
D
A
B
Z
Y
R
GND
V
CC
V
CC
Z
Y
ADM4854/ADM4855/
ADM4856/ADM4857
ADM4854/ADM4855/
ADM4856/ADM4857
ADM4850 to ADM4857 Data Sheet
Rev. F | Page 14 of 16
HIGH RECEIVER INPUT IMPEDANCE
The input impedance of the ADM4850/ADM4851/ADM4852/
ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 receivers
is 96 k, which is eight times higher than the standard RS-485 unit
load of 12 k. This 96 kimpedance enables a standard driver
to drive 32 unit loads or to be connected to 256 ADM4850/
ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/
ADM4856/ADM4857 receivers. An RS-485 bus, driven by a
single standard driver, can be connected to a combination of
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 devices and standard unit
load receivers, up to an equivalent of 32 standard unit loads.
THREE-STATE BUS CONNECTION
The half-duplex devices (ADM4850/ADM4852/ADM4853)
have a driver enable pin (DE) that enables the driver outputs
when taken high, or puts the driver outputs into a high
impedance state when taken low. Similarly, the half-duplex devices
have an active low receiver enable pin (
RE
). Taking this pin low
enables the receiver, whereas taking it high puts the receiver
outputs into a high impedance state, which allows several driver
outputs to be connected to an RS-485 bus. Note that only one
driver must be enabled at a time, but that many receivers can be
enabled.
SHUTDOWN MODE
The ADM4850/ADM4852/ADM4853 have a low power
shutdown mode, which is enabled by taking
RE
high and DE
low. If shutdown mode is not used, the fact that DE is active
high and
RE
is active low offers a convenient way of switching the
device between transmit and receive by tying DE and
RE
together.
If DE is driven low and
RE
is driven high for less than 50 ns, the
devices are guaranteed not to enter shutdown mode. If DE is
driven low and
RE
is driven high for at least 3000 ns, the devices
are guaranteed to enter shutdown mode.
FAIL-SAFE OPERATION
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 offer true fail-safe operation
while remaining fully compliant with the ±200 mV EIA/TIA-485
standard. A logic high receiver output generates when the
receiver inputs are shorted together or open circuit, or when
they are connected to a terminated transmission line with all
drivers disabled. This logic high is done by setting the receiver
threshold between −30 mV and −200 mV. If the differential
receiver input voltage (A − B) is greater than or equal to
−30 mV, RO is logic high. If (A − B) is less than or equal to
−200 mV, RO is logic low. In the case of a terminated bus
with all transmitters disabled, the differential input voltage
of the receiver is pulled to 0 V by the internal circuitry of
the ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857, which results in a logic high
with 30 mV minimum noise margin.
CURRENT LIMIT AND THERMAL SHUTDOWN
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 incorporate two protection
mechanisms to guard the drivers against short circuits, bus
contention, or other fault conditions. The first is a current limiting
output stage, which protects the driver against short circuits
over the entire common-mode voltage range by limiting the
output current to approximately 70 mA. Under extreme fault
conditions where the current limit is not effective, a thermal
shutdown circuit puts the driver outputs into a high impedance
state if the die temperature exceeds 150°C, and does not turn
them back on until the temperature falls to 130°C.
Data Sheet ADM4850 to ADM4857
Rev. F | Page 15 of 16
OUTLINE DIMENSIONS
Figure 31. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Figure 32. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
F
igure 33. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
C
OPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.55
1.45
1.35
1.84
1.74
1.64
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-229-WEED
12-07-2010-A
PIN 1
INDICATOR
(R 0.15)

ADM4856AR-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
IC TXRX RS485/422 2.5MBPS 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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