M34C02
4/28
SUMMARY DESCRIPTION
The M34C02 is a 2Kbit serial EEPROM memory
able to lock permanently the data in its first half
(from location 00h to 7Fh). This facility has been
designed specifically for use in DRAM DIMMs (du-
al interline memory modules) with Serial Presence
Detect. All the information concerning the DRAM
module configuration (such as its access speed,
its size, its organization) can be kept write protect-
ed in the first half of the memory.
This bottom half of the memory area can be write-
protected using a specially designed software
write protection mechanism. By sending the de-
vice a specific sequence, the first 128 Bytes of the
memory become permanently write protected.
Care must be taken when using this sequence as
its effect cannot be reversed. In addition, the de-
vice allows the entire memory area to be write pro-
tected, using the WC
input (for example by tieing
this input to V
CC
).
These I
2
C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 256x8 bits.
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
ECOPACK® packages are Lead-free and RoHS
compliant.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
Figure 2. Logic Diagram
I
2
C uses a two wire serial interface, comprising a
bi-directional data line and a clock line. The device
carries a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
2
C bus definition to
access the memory area and a second Device
Type Identifier Code (0110) to access the Protec-
tion Register. These codes are used together with
three chip enable inputs (E2, E1, E0) so that up to
eight 2Kbit devices may be attached to the I²C bus
and selected individually.
The device behaves as a slave device in the I
2
C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW
bit (as described in
Table 3.), terminated by an acknowledge bit.
When writing data to the memory, the memory in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af-
ter a NoAck for READ.
Figure 3. DIP, TSSOP and MLP Connections
(Top View)
Note: See PACKAGE MECHANICAL section for package dimen-
sions, and how to identify pin-1.
Table 2. Signal Names
AI01931
3
E0-E2 SDA
V
CC
M34C02
WC
SCL
V
SS
E0, E1, E2 Chip Enable
SDA Serial Data
SCL Serial Clock
WC
Write Control
V
CC
Supply Voltage
V
SS
Ground
SDAV
SS
SCL
WCE1
E0 V
CC
E2
AI01932C
M34C02
1
2
3
4
8
7
6
5
