NCP81074BMNTBG

NCP81074A, NCP81074B
www.onsemi.com
10
PCB LAYOUT RECOMMENDATION
Proper component placement is extremely important in
high current, fast switching applications to provide
appropriate device operation and design robustness. The
NCP81074 gate driver exhibits a powerful output stage
enabling large peak currents with fast rise and fall times.
Eventhough the NCP81074 provides a split output
configuration for slew rate control, a proper PCB layout is
crucial to ensure maximum performance. The following
circuit layout guidelines are strongly recommended when
designing with the NCP81074.
Place the driver close to the power MOSFET in order to
have a low impedance path between the output pins and
the gate. Keep the traces short and wide to minimize the
parasitic inductance and accommodate for high peak
currents.
Place the decoupling capacitor close to the gate drive
IC. Placing the VDD capacitor close to the pin and
ground improves noise filtering. This capacitor supplies
high peak currents during the turn−on transition of the
MOSFET. Using a low ESL chip capacitor is highly
recommended.
Keep a tight turn−on turn−off current loop paths to
minimize parastic inductance. High di/dt will induce
voltage spikes on the output pin and the MOSFET gate.
Parallel the source and return signals taking advantage
of flux cancellation.
Since the NCP81074 is a 2x2mm package driving high
peak currents into capacitive loads, adding a shielding
ground plane helps in power dissipation and noise
blocking. The ground plane should not be a current
carrying path to any of the current loops.
Any unused pin, should be pulled to either rail
depending on the functionality of the pin to avoid any
malfunction on the output. Please refer to the pin
description table for more information.
Figure 24.
NCP81074A, NCP81074B
www.onsemi.com
11
PACKAGE DIMENSIONS
DFN8 2x2
CASE 506AA
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
E
B
C0.15
PIN ONE
2X
REFERENCE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
L
(A3)
D2
E2
C
C0.15
C0.10
C0.08
NOTE 4
A1
SEATING
PLANE
e/2
e
8X
K
NOTE 3
b
8X
0.10 C
0.05 C
A
BB
DIM MIN MAX
MILLIMETERS
A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b 0.20 0.30
D 2.00 BSC
D2 1.10 1.30
E 2.00 BSC
E2 0.70 0.90
e 0.50 BSC
K
L 0.25 0.35
1
4
8
5
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
L
DETAIL B
MOLD CMPDEXPOSED Cu
OPTIONAL
CONSTRUCTION
DETAIL B
DETAIL A
L1 −− 0.10
0.30 REF
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.30
0.50
0.50
8X
DIMENSIONS: MILLIMETERS
0.30
PITCH
8X
1
PACKAGE
OUTLINE
RECOMMENDED
0.90
1.30
NCP81074A, NCP81074B
www.onsemi.com
12
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) Z
S
X
S
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒ
mm
inches
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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NCP81074/D
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NCP81074BMNTBG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Gate Drivers SINGLE CHANNEL 10A H
Lifecycle:
New from this manufacturer.
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