6
LT3433
3433f
UU
U
PI FU CTIO S
V
FB
(Pin 7): Error Amplifier Inverting Input. The noninvert-
ing input of the error amplifier is connected to an internal
1.231V reference. The V
FB
pin is connected to a resistor
divider from the converter output. Values for the resistor
connected from V
OUT
to V
FB
(R
FB1
) and the resistor con-
nected from V
FB
to ground (R
FB2
) can be calculated to pro-
gram converter output voltage (V
OUT
) via the following
relation:
V
OUT
= 1.231 • (R
FB1
+ R
FB2
)/R
FB2
The V
FB
pin input bias current is 35nA, so use of extremely
high value feedback resistors could cause a converter
output that is slightly higher than expected. Bias current
error at the output can be estimated as:
∆V
OUT(BIAS)
= 35nA • R
FB1
The voltage on V
FB
also controls the LT3433 oscillator
frequency through a “frequency-foldback” function. When
the V
FB
pin voltage is below 0.8V, the oscillator runs slower
than the 200kHz typical operating frequency. The oscilla-
tor frequency slows with reduced voltage on the pin, down
to 50kHz when V
FB
= 0V.
The V
FB
pin voltage also controls switch current limit
through a “current-limit foldback” function. At V
FB
= 0V, the
maximum switch current is reduced to half of the normal
value. The current limit value increases linearly until V
FB
reaches 0.6V when the normal maximum switch current
level is restored. The frequency and current-limit foldback
functions add robustness to short-circuit protection and
help prevent inductor current runaway during start-up.
SS (Pin 10): Soft Start. Connect a capacitor (C
SS
) from this
pin to ground. The output voltage of the LT3433 error
amplifier corresponds to the peak current sense amplifier
output detected before resetting the switch output(s). The
soft-start circuit forces the error amplifier output to a zero
peak current for start-up. A 5µA current is forced from the
SS pin onto an external capacitor. As the SS pin voltage
ramps up, so does the LT3433 internally sensed peak cur-
rent limit. This forces the converter output current to ramp
from zero until normal output regulation is achieved. This
function reduces output overshoot on converter start-up.
The time from V
SS
= 0V to maximum available current can
be calculated given a capacitor C
SS
as:
t
SS
= (2.7 • 10
5
)C
SS
or 0.27s/µF
SHDN (Pin 11): Shutdown. If the SHDN pin is externally
pulled below 0.5V, low current shutdown mode is initiated.
During shutdown mode, all internal functions are disabled,
and I
CC
is reduced to 10µA. This pin is intended to receive
a digital input, however, there is a small amount of input
hysteresis built into the SHDN circuit to help assure glitch-
free mode switching. If shutdown is not desired, connect
the SHDN pin to V
IN
.
V
BIAS
(Pin 12): Internal Local Supply. Much of the LT3433
circuitry is powered from this supply, which is internally
regulated to 2.5V through an on-board linear regulator.
Current drive for this regulator is sourced from the V
IN
pin.
The V
BIAS
supply is short-circuit protected to 5mA.
The V
BIAS
supply only sources current, so forcing this pin
above the regulated voltage allows the use of external power
for much of the LT3433 circuitry. When using external drive,
this pin should be driven above 3V to assure the internal
supply is completely disabled. This pin is typically diode-
connected to the converter output to maximize conversion
efficiency. This pin must be bypassed with at least a 0.1µF
ceramic capacitor to SGND.
V
OUT
(Pin 13): Converter Output Pin. This pin voltage is
compared with the voltage on V
IN
internally to control
operation in single or 2-switch mode. When the ratios of
the two voltages are such that a >75% duty cycle is required
for regulation, the low side switch is enabled. Drive bias for
the low side switch is also derived directly from this pin.
PWRGND (Pin 14): High Current Ground Reference. This
is the current return for the low side switch and corresponds
to the emitter of the low side switch transistor.
SW_L (Pin 15): Ground Referenced Switch Output. This pin
is the collector of the low side switch transistor. The low
side switch shorts the SW_L pin to PWRGND when enabled.
The series impedance of the ground-referenced switch is
0.6Ω.
Exposed Pad (Pin 17): Exposed Pad must be soldered to
PCB ground for optimal thermal performance.
