Data Sheet AD8315
Rev. D | Page 3 of 22
SPECIFICATIONS
V
S
= 2.7 V, T = 25°C, 52.3 Ω termination on RFIN, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
OVERALL FUNCTION
Frequency Range
1
To meet all specifications 0.1 2.5 GHz
Input Voltage Range ±1 dB log conformance, 0.1 GHz −57 −11 dBV
Equivalent dBm Range −44 +2 dBm
Logarithmic Slope
2
0.1 GH 21.5 24 25.5 mV/dB
Logarithmic Intercept
2
0.1 GHz −79 −70 −64 dBV
Equivalent dBm Level −66 −57 −51 dBm
RF INPUT INTERFACE Pin RFIN
Input Resistance
3
0.1 GHz 2.8 kΩ
Input Capacitance
3
0.1 GHz 0.9 pF
OUTPUT Pin VAPC
Minimum Output Voltage V
SET
≤ 200 mV, ENBL high 0.25 0.27 0.3 V
ENBL low 0.02 V
Maximum Output Voltage R
L
≥ 800 Ω 2.45 2.6 V
vs. Temperature
4
85°C, V
POS
= 3 V, I
OUT
= 6 mA 2.54 V
General Limit 2.7 V ≤ V
POS
≤ 5.5 V, R
L
= ∞ V
POS
− 0.1 V
Output Current Drive Source/Sink 5/200 mA/μA
Output Buffer Noise 25 nV√Hz
Output Noise RF input = 2 GHz, 0 dBm, f
NOISE
= 100 kHz, C
FLT
= 220 pF 130 nV/√Hz
Small Signal Bandwidth 0.2 V to 2.6 V swing 30 MHz
Slew Rate 10% to 90%, 1.2 V step (V
SET
), open loop
5
13 V/μs
Response Time FLTR = open, see Figure 27 150 ns
SETPOINT INTERFACE Pin VSET
Nominal Input Range Corresponding to central 50 dB 0.25 1.4 V
Logarithmic Scale Factor 43.5 dB/V
Input Resistance 100 kΩ
Slew Rate 16 V/μs
ENABLE INTERFACE Pin ENBL
Logic Level to Enable Power 1.8 V
POS
V
Input Current when Enable
High
20 μA
Logic Level to Disable Power 0.8 V
Enable Time
Time from ENBL high to V
APC
within 1% of final value,
V
SET
≤ 200 mV, refer to Figure 24
4 5 μs
Disable Time
Time from ENBL low to V
APC
within 1% of final value,
V
SET
≤ 200 mV, refer to Figure 24
8 9 μs
Power-On/Enable Time
Time from VPOS/ENBL high to V
APC
within 1% of final value,
V
SET
≤ 200 mV, refer to Figure 29
2 3 μs
Time from VPOS/ENBL low to V
APC
within 1% of final value,
V
SET
≤ 200 mV, refer to Figure 29
100 200 ns
