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N08L63W2AB27I

P1-P3P4-P6P7-P9P10-P10
N08L63W2A
©2008 SCILLC. All rights reserved. Publication Order Number:
July 2008 - Rev. 8 N08L63W2A/D
8Mb Ultra-Low Power Asynchronous CMOS SRAM
512K × 16 bit
Overview
The N08L63W2A is an integrated memory device
containing a 8 Mbit Static Random Access Memory
organized as 524,288 words by 16 bits. The device
is designed and fabricated using ON
Semiconductor’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with two chip enable
(CE1
and CE2) controls and output enable (OE) to
allow for easy memory expansion. Byte controls
(UB
and LB) allow the upper and lower bytes to be
accessed independently and can also be used to
deselect the device. The N08L63W2A is optimal
for various applications where low-power is critical
such as battery backup and hand-held devices.
The device can operate over a very wide
temperature range of -40
o
C to +85
o
C and is
available in JEDEC standard packages compatible
with other standard 512Kb x 16 SRAMs
Features
• Single Wide Power Supply Range
2.3 to 3.6 Volts
• Very low standby current
4.0µA at 3.0V (Typical)
• Very low operating current
2.0mA at 3.0V and 1µs(Typical)
• Very low Page Mode operating current
1.0mA at 3.0V and 1µs (Typical)
• Simple memory control
Dual Chip Enables (CE1
and CE2)
Byte control for independent byte operation
Output Enable (OE
) for memory expansion
• Low voltage data retention
Vcc = 1.8V
• Very fast output enable access time
25ns OE
access time
• Very fast Page Mode access time
t
AAP
= 25ns
• Automatic power down to standby mode
• TTL compatible three-state output driver
Pin Configuration
Product Family
Part Number Package Type
Operating
Temperature
Power
Supply
(Vcc)
Speed
Standby
Current (I
SB
),
Typical
Operating
Current (Icc),
Typical
N08L63W2AB 48 - BGA
-40
o
C to +85
o
C
2.3V - 3.6V
70ns@2.7V
85ns @ 2.3V
4 µA2 mA @ 1MHz
N08L63W2AB2 48 - BGA Green
123456
A
LB OE
A
0
A
1
A
2
CE2
B
I/O
8
UB
A
3
A
4
CE1
I/O
0
C
I/O
9
I/O
10
A
5
A
6
I/O
1
I/O
2
D
V
SS
I/O
11
A
17
A
7
I/O
3
V
CC
E
V
CC
I/O
12
NC
A
16
I/O
4
V
SS
F
I/O
14
I/O
13
A
14
A
15
I/O
5
I/O
6
G
I/O
15
NC
A
12
A
13
WE
I/O
7
H
A
18
A
8
A
9
A
10
A
11
NC
48 Pin BGA (top)
8 x 10 mm
Pin Descriptions
Pin Name Pin Function
A
0
-A
18
Address Inputs
WE
Write Enable Input
CE1
, CE2 Chip Enable Input
OE
Output Enable Input
LB
Lower Byte Enable Input
UB
Upper Byte Enable Input
I/O
0
-I/O
15
Data Inputs/Outputs
V
CC
Power
V
SS
Ground
NC Not Connected
Rev. 8 | Page 2 of 10 | www.onsemi.com
N08L63W2A
Functional Block Diagram
Functional Description
CE1 CE2 WE OE UB LB
I/O
0
- I/O
15
1
1. When UB and LB are in select mode (low), I/O
0
- I/O
15
are affected as shown. When LB only is in the select mode only I/O
0
- I/O
7
are affected as shown. When UB
is in the select mode only I/O
8
- I/O
15
are affected as shown.
MODE POWER
HXXXXX High Z
Standby
2
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
Standby
XLXXXX High Z
Standby
2
Standby
XXXXHH High Z
Standby
2
Standby
LHL
X
3
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
L
1
L
1
Data In
Write
3
Active
LHHL
L
1
L
1
Data Out
Read
Active
LHHH
L
1
L
1
High Z Active Active
Capacitance
1
1. These parameters are verified in device characterization and are not 100% tested
Item Symbol Test Condition Min Max Unit
Input Capacitance
C
IN
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8pF
I/O Capacitance
C
I/O
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8pF
Address
Inputs
A0 - A3
Address
Inputs
A4 - A18
Word
Address
Decode
Logic
32K Page
x 16 word
x 16 bit
RAM Array
Word Mux
Input/
Output
Mux
and
Buffers
Page
Address
Decode
Logic
Control
Logic
CE1
CE2
WE
OE
UB
LB
I/O0 - I/O7
I/O8 - I/O15
Rev. 8 | Page 3 of 10 | www.onsemi.com
N08L63W2A
Absolute Maximum Ratings
1
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item Symbol Rating Unit
Voltage on any pin relative to V
SS
V
IN,OUT
–0.3 to V
CC
+0.3
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
–0.3 to 4.5 V
Power Dissipation
P
D
500 mW
Storage Temperature
T
STG
–40 to 125
o
C
Operating Temperature
T
A
-40 to +85
o
C
Soldering Temperature and Time
T
SOLDER
260
o
C, 10sec
o
C
Operating Characteristics (Over Specified Temperature Range)
Item Symbol Test Conditions Min.
Typ
1
1. Typical values are measured at Vcc=Vcc Typ., T
A
=25°C and not 100% tested.
Max Unit
Supply Voltage
V
CC
2.3 3.0 3.6 V
Data Retention Voltage
V
DR
Chip Disabled
3
1.8 V
Input High Voltage
V
IH
1.8
V
CC
+0.3
V
Input Low Voltage
V
IL
–0.3 0.6 V
Output High Voltage
V
OH
I
OH
= 0.2mA V
CC
–0.2
V
Output Low Voltage
V
OL
I
OL
= -0.2mA
0.2 V
Input Leakage Current
I
LI
V
IN
= 0 to V
CC
0.5 µA
Output Leakage Current
I
LO
OE = V
IH
or Chip Disabled
0.5 µA
Read/Write Operating Supply Current
@ 1 µs Cycle Time
2
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
I
CC1
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
2.0 3.0 mA
Read/Write Operating Supply Current
@ 70 ns Cycle Time
2
I
CC2
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
9.0 15.0 mA
Page Mode Operating Supply Current
@ 70ns Cycle Time
2
(Refer to Power
Savings with Page Mode Operation
diagram)
I
CC3
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
2.0 3.0 mA
Read/Write Quiescent Operating Sup-
ply Current
3
3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all
inputs must be within 0.2 volts of either VCC or VSS.
I
CC4
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0,
f = 0
3.0 mA
Maximum Standby Current
3
I
SB1
V
IN
= V
CC
or 0V
Chip Disabled
t
A
= 85
o
C, V
CC
= 3.6 V
4.0 20.0 µA
Maximum Data Retention Current
3
I
DR
Vcc = 1.8V, V
IN
= V
CC
or 0
Chip Disabled, t
A
= 85
o
C
10 µA
P1-P3P4-P6P7-P9P10-P10

N08L63W2AB27I

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Manufacturer:
ON Semiconductor
Description:
SRAM 8MB 3V LOW PWR SRAM
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