N08L63W2AB27I

Rev. 8 | Page 4 of 10 | www.onsemi.com
N08L63W2A
Power Savings with Page Mode Operation (WE = V
IH
)
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
Page Address (A4 - A18)
LB
, UB
OE
CE1
CE2
Word Address (A0 - A3)
Open page
Word 1 Word 2
Word 16
...
Rev. 8 | Page 5 of 10 | www.onsemi.com
N08L63W2A
Timing Test Conditions
Item
Input Pulse Level
0.1V
CC
to 0.9 V
CC
Input Rise and Fall Time 5ns
Input and Output Timing Reference Levels
0.5 V
CC
Output Load CL = 30pF
Operating Temperature
-40 to +85
o
C
Timing
Item Symbol
2.3 - 3.6 V 2.7 - 3.6 V
Units
Min. Max. Min. Max.
Read Cycle Time
t
RC
85 70 ns
Address Access Time (Random Access)
t
AA
85 70 ns
Address Access Time (Page Mode)
t
AAP
30 25 ns
Chip Enable to Valid Output
t
CO
85 70 ns
Output Enable to Valid Output
t
OE
30 25 ns
Byte Select to Valid Output
t
LB
, t
UB
85 70 ns
Chip Enable to Low-Z output
t
LZ
10 10 ns
Output Enable to Low-Z Output
t
OLZ
55ns
Byte Select to Low-Z Output
t
LBZ
, t
UBZ
10 10 ns
Chip Disable to High-Z Output
t
HZ
020020ns
Output Disable to High-Z Output
t
OHZ
020020ns
Byte Select Disable to High-Z Output
t
LBHZ
, t
UBHZ
020020ns
Output Hold from Address Change
t
OH
55ns
Write Cycle Time
t
WC
85 70 ns
Chip Enable to End of Write
t
CW
50 50 ns
Address Valid to End of Write
t
AW
50 50 ns
Byte Select to End of Write
t
LBW
, t
UBW
50 50 ns
Write Pulse Width
t
WP
40 40 ns
Address Setup Time
t
AS
00ns
Write Recovery Time
t
WR
00ns
Write to High-Z Output
t
WHZ
20 20 ns
Data to Write Time Overlap
t
DW
40 40 ns
Data Hold from Write Time
t
DH
00
ns
End Write to Low-Z Output
t
OW
55ns
Rev. 8 | Page 6 of 10 | www.onsemi.com
N08L63W2A
Timing of Read Cycle (CE1 = OE = V
IL
, WE = CE2 = V
IH
)
Timing Waveform of Read Cycle (WE
=V
IH
)
Address
Data Out
t
RC
t
AA,
t
AAP
t
OH
Data ValidPrevious Data Valid
Address
LB
, UB
OE
Data Valid
t
RC
t
AA,
t
AAP
t
CO
t
HZ
t
OHZ
t
LBHZ,
t
UBHZ
t
OLZ
t
OE
t
LZ
High-Z
Data Out
t
LB,
t
UB
t
LBLZ,
t
UBLZ
CE1
CE2

N08L63W2AB27I

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
SRAM 8MB 3V LOW PWR SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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