NCP1562A, NCP1562B
http://onsemi.com
13
t
D(trail)
t
D(lead)
t
D(trail)
t
D(lead)
t
D(trail)
t
D(lead)
D, DUTY CYCLE (%)
90
3010
R
T
, TIMING RESISTOR (kΩ)
85
75
70
65
60
55
50
45
40
80
50 70 90 110
V
AUX
=12V
T
J
=25C
R
D
= 69.8 kΩ
C
T
= 150 pF
C
T
= 220 pF
C
T
= 470 pF
D, DUTY CYCLE (%)
90
1501251007550250-- 2 5-- 5 0
T
J
, JUNCTION TEMPERATURE (C)
Figure 24. Oscillator Frequency
vs. Timing Resistor
V
AUX
=12V
R
D
= 69.8 kΩ
85
75
70
65
60
55
50
45
40
80
R
T
= 15.8 kΩ,C
T
= 220 pF
R
T
=11.8kΩ,C
T
= 470 pF
R
T
=20kΩ,C
T
= 150 pF
I
SS(C)
, CHARGE CURRENT (mA)
15
1501251007550250-- 2 5-- 5 0
T
J
, JUNCTION TEMPERATURE (C)
V
AUX
=12V
14
12
11
10
9
8
7
6
5
13
DISCHARGE (V
UVOV
=0V)
CHARGE
I
SS(D)
, DISCHARGE CURRENT (mA)
t
D
, OVERLAP TIME DELAY (ns)
500
800
R
D
, DELAY RESISTOR (kΩ)
Figure 25. Duty Cycle
vs. Timing Resistor
450
350
300
250
200
150
100
50
0
400
160 240 320 400
V
AUX
=12V
T
J
=25C
LEADING
TRAILING
150
140
130
120
110
100
90
80
70
60
50
t
D
, OVERLAP TIME DELAY (ns)
400
Figure 26. Duty Cycle
vs. Junction Temperature
350
250
200
150
100
50
0
300
V
AUX
=12V
T
J
, JUNCTION TEMPERATURE (C)
1501251007550250-- 2 5-- 5 0
f
OSC
, OSCILLATOR FREQUENC
Y
(kHz)
3010
R
T
, TIMING RESISTOR (kΩ)
800
700
600
500
400
300
200
100
900
50 70 90 110
V
AUX
=12V
T
J
=25C
C
T
= 150 pF
C
T
= 220 pF
C
T
= 470 pF
Figure 27. Soft --Start/Stop Charge and Discharge
Currents vs. Junction Temperature
Figure 28. Overlap Time Delay
vs. Delay Resistor
Figure 29. Overlap Time Delay
vs. Junction Temperature
R
D
= 200 kΩ
R
D
=20kΩ
R
D
= 69.8 kΩ
0
NCP1562A, NCP1562B
http://onsemi.com
14
SINK, V
out2
=1V
SOURCE, V
out2
=11V
R
SNK/SRC
, OUTPUT 2 DRIVE RESISTANCE (Ω)
1501251007550250-- 2 5-- 5 0
T
J
, JUNCTION TEMPERATURE (C)
V
AUX
=12V
17
16
15
14
13
12
11
6
18
R
IN(VEA)
,V
EA
INPUT RESISTANCE (kΩ)
50
1501251007550250-- 2 5-- 5 0
T
J
, JUNCTION TEMPERATURE (C)
45
35
30
25
20
15
10
5
0
40
V
EA(L)
, PWM COMPARATOR LOWER
INPUT THRESHOLD (V)
1.5
1501251007550250-- 2 5-- 5 0
T
J
, JUNCTION TEMPERATURE (C)
1.4
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
1.3
R
SNK/SRC
, OUTPUT 1 DRIVE RESISTANCE (Ω)
10
1501251007550250-- 2 5-- 5 0
T
J
, JUNCTION TEMPERATURE (C)
Figure 30. Output 1 Drive Resistance
vs. Junction Temperature
V
AUX
=12V
9
7
6
5
4
3
2
1
0
8
SINK, V
out1
=1V
SOURCE, V
out1
=11V
Figure 31. Output 2 Drive Resistance
vs. Junction Temperature
Figure 32. V
EA
Input Resistance
vs. Junction Temperature
Figure 33. PWM Comparator Lower Input Threshold
vs. Junction Temperature
V
EA
=0V
10
9
8
7
NCP1562A, NCP1562B
http://onsemi.com
15
DETAILED OPERATING DESCRIPTION
The NCP1562x is a family of voltage mode controllers
designed for dc--dc converters requiring high--efficiency
and low parts count. These controllers incorporate two in
phase outputs with an adjustable overlap delay. The main
output is designed for driving a forward converter primary
MOSFET. The secondary output is designed for driving an
active clamp circuit MOSFET, a synchronous rectifier on
the secondary side, or an asymmetric half bridge circuit.
Two distinctive fe atures of the NCP1562 are the
soft--stop and a cycle skip overcurrent detector with a time
threshold. The soft--stop powers down the converte r in a
controlled manner after a fault is detected. The cycle skip
timer disables the converter if a continuous overcurrent
condition is present.
The NCP1562 reduces component count and system size
by incorporating high accuracy on critical specifications
such as programmable maximum duty cyc le, undervoltage
detector and overcurrent threshold. Additional features
found in the NCP1562 include line feedforward,
bidirectional frequenc y synchronizat ion up to 1.0 MHz,
cycle--by--cycle current limit with leading edge blanking
(LEB), independe nt under and overvoltage detectors,
internal startup circuit and soft--start.
SOFT--STOP AND SOFT--START
The NCP1562 incorporates a novel soft--stop and
soft--start architec ture that c ombines soft--start and
soft--stop functions on a single pin.
Soft--stop reduces the duty cycle until it reaches 0% once
a fault is detec ted. By slowly reducing the duty cycle during
power down, the active clamp capacitor (C
clamp
)is
discharged. This prevents oscillations between the power
transformer and C
clamp
, and ensures the converter turns off
in a predictable state.
Soft--start slowly increases the duty cycle during power
up allowing the controller to gradually reach steady state
operation. Combined, both features reduce system stress
and power surges.
The duty cycle is controlled by compa ring the SS
capacitor voltage (V
SS
) to the Feedforward (FF) Ramp.
Soft--start or soft--stop is implemented by slowly charging
or discharging the capacitor on the SS pin. OUT1 is
disabled once the FF Ramp exceeds V
SS
. The soft--start
charge current is 10 mA and the soft--stop discharge current
is 100 mA, guaranteeing a faster turn OFF time.
The converter enters a soft--stop sequence if an
undervoltage, overvoltage, cycle skip or thermal shutdown
condition is detected. Once the converter enters the
soft--stop mode, it will stay in soft--stop mode until V
SS
reaches 0.2 V even if the fault is removed prior to reaching
0.2 V.
The preset 1:10 charge:discharge ratio can be reduced by
placing an external resistor between the V
REF
and SS pins.
The resistor should be sized such that t he total charge
current does not exceed 100 mA. Otherwise the converter
will not be able to complete a soft--stop sequence.
Depending on the converter state, a soft--stop sequence
is handled differently to ensure the fastest response time
and prevent system malfunction. If a soft--stop sequence
starts before V
SS
exceeds the maximum voltage clamp of
the FF Ramp (typ. 3.0 V) and the PWM Comparator (V
EA
)
is not yet controlling the duty cycle, a controlled discharge
of C
SS
commences immediately, as shown in Figure 34.
However, if V
EA
is controlling the duty cycle, C
SS
is
discharged until soft--stop sets a duty cycle equal to the duty
cycle set by V
EA
. A controlled discharge commences
afterwa rds, as shown in Figure 35. If V
SS
exceeds the FF
Ramp and the V
EA
is not controlling the duty cycle, V
SS
is
forced to the peak voltage of the FF Ramp, before starting
a cont rolled discharge of C
SS
, as shown in Figure 36. The
duty c ycle set at the beginning of the soft--stop event never
exceeds the duty cycle prior to the soft--stop event.
Figure 34. Soft --Stop Before Soft --Start
is Complete and V
EA
is Open.
(V
EA
is not controlling the duty cycle)
V
EA
V
SS
FF Ramp
Figure 35. Soft --Stop Behavior when V
EA
Controls the Duty Cycle.
V
SS
V
X
=V
EA
-- V
f
V
EA

NCP1562ADR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers HI PERF RESET PWM CONTLR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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