NCP1562ADR2G Datasheet NCP1562ADBR2G, NCP1562BDR2G, NCP1562ADR2G | P19-P21

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(patent pending). This architecture allows both the UV and

OV levels to be set independently. Both t he UV and OV

detectors have a 100 mV hysteresis.

The line voltage is sampled using a resistor divider as

shown in Figure 42.

OV Comparator

OVCOMP

3.0 V

UV Comparator

UVCOMP

2.0 V

2.5 V

UVOV

offset(UVOV)

Figure 42. Line UVOV Detectors

A UV condition exists if the UVOV voltage is below

, typically 2.0 V. The ratio of R1 and R2 determinesthe

UV turn threshold. Once the UVOV voltage exceeds 2.5 V,

an internal current source (I

offset(UVOV)

) sinks 50 mA into

the UVOV pin. This will clamp the UVOV voltage at 2.5 V

while the current across R1 i s less than I

offset(UVOV)

.Ifthe

input voltage continues to increase, the 50 mA source will

be overridden and the voltage at the UVOV pin will

increase. An OV condition exists if the UVOV voltage

exceeds V

, typically 3.0 V. Figure 43 shows the

relationship between UVOV and V

Figure 43. UVOV Detectors Typical Waveforms

Time

UVOV

(V)

OVCOMP

UVCOMP

UVOV

While the internal current source is disabled, the UVOV

voltage is solely determined by the ratio of R1 and R2. The

input voltage at which the converter turns ON is given by

Equation 1. Once the i nternal current source is enabled, the

absolute value of R1 together with the ratio of R1 and R2

determine the turn OFF threshold as shown in Equation 2.

in(UV)

= V

+ R

)

(eq. 1)

in(OV)

= V

+ R

)

+ (I

offset(UVOV)

× R1)

(eq. 2)

The undervoltage threshold is t rimmed during

manufacturing to obtain 3% accuracy allowing a tighter

power stage design.

Once the line voltage is within the operating range, and

AUX

reaches V

AUX(on)

, the outputs are enabled and a

soft--start sequence commences. If a UV or OV fault is

detected afterwards, the converter enters a soft--stop mode .

A small capacitor is require d (>1000 pF) from the

UVOV pin to GND to prevent oscillation of the UVOV pin

and filter line transients.

Line Feedforward

The NCP1562 incorporates line feedforwa rd (FF) to

limit the maximum volt--second product. It is the line

voltage times the ON time. This limit prevent saturation of

the transformer in forward and flyback topol ogies. Another

advantage of feedforward is a controller frequency gai n

independent of line voltage . A constant gain facilitates

frequenc y compensation of the converter.

Feed fo rw ar d is implemented by generating a ramp

proportional to V

and comparing it to the error signal. The

error signal solely controls the duty cycle while the input

voltage is fixed. If the line voltage changes, the FF Ramp

slo pe chan ges and duty cycle is immediately adjusted in s tead

of waiting for the change to propagate around the feedback

loop and be reflected back on the error sign al.

The FF Ramp is generated with an R--C (R

) divider

from the input l ine as shown in Figure 44. The divider is

selected such that the FF Ramp reaches 3.0 V in the desired

maximum ON time. The FF Ramp terminates by

effective ly grounding C

during the converter OFF time.

This can be triggered by the FF Ramp reaching 3.0 V, or

any other condition that limits the duty cycle.

To PWM and VS

Comparators

FF Reset

FF(D)

RFF

Figure 44. Feed Forward Ramp Generation

The FF pin is effectively grounded during power or

during standby mode to prevent the FF pi n from charging

up to V

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The minimum value of R

is determined by the FF

Ramp discharge current (I

FF(D)

). The current through R

RFF

) should be at least ten times smaller than I

FF(D)

for a

sharp FF Ramp transition. Equations 3 and 4 are used to

determine R

and C

0.1 × I

FF(D)

≤ R

(eq. 3)



-- 3 V



× f × R

(eq. 4)

where, f is the operating frequency. It is recommended to

bias the FF circuit with enough current to provide good

noise immunity.

PWM Comparator

In steady state operation, the PWM Comparator adjusts

the dut y cycle by comparing the error signal to t he FF

Ramp. The error signal is fed into the V

pin. The V

can be driven directly with an optocoupler without the need

of an external pul lup resistor as shown in Figure 45. In

some instances, it may be required to have a pullup resistor

smaller than the internal resistor (R4) to adjust the gain of

the isolation stage. This is easily accomplished by

connec ting an external resistor (R

) in parallel with R4.

is connected between the V

REF

and V

pins. The

effective pullup resistance is the parallel combination of

R4 and R

PWM

Comparator

0.2 V

270 kΩ

2kΩ

REF

(Optional)

Feedback

Signal

FF Ramp

Figure 45. Optocoupler Driving V

Input

20 kΩ

The drive of the V

pin is simplified by internally

incorporating a series diode and resistor. The series diode

provides a 0.7 V offset between the V

input and t he

PWM Comparator inverting i nput. It allows reaching zero

duty cycle without the need of pulling the V

pin all the

way to GND. The outputs are enabled if the V

voltage is

approximately 0.5 V above the valley of the FF Ramp.

Outputs

The NCP1562 has two in--phase output drivers with an

adjustable overlap delay (t

). The main output, OUT1, has

a source re sistance of 4.0 Ω (typ) and a sink resistance of

2.5 Ω (typ). The secondary output, OUT2, has a source and

a sink resistance of 12 Ω (typ). OUT1 is rated at a

maximum of 2.0 A and OUT2 is rated at a maximum of

1.0 A. If a higher drive capability is required, an external

driver sta ge can be easily added as shown in Figure 46.

AUX

Output

Figure 46. Discrete Boost Drive Stage

OUT1

OUT2

OUT1 drives the main MOSFET, and OUT2 drives a low

side P --Channel active clamp MOSFET. A high side

N--Channel active clamp MOSFET or a synchronous

rectifier can also be driven by inverting OUT2. OUT2 is

purposely sized smaller than OUT1 because the active

clamp MOSFET only sees the magnetizing current.

There fore, a smaller active clamp MOSFET with less input

capacitance can be used compared to the main switch.

Once V

AUX

reaches V

AUX(on)

(typically 10.3 V), the

internal startup circuit is disabled and the outputs are

enabled if no faults are present. Otherwise, the outputs

remain disabled until the fault is removed and V

AUX

reachesV

AUX(on)

. The outputs are disabled after a soft--stop

sequence if V

AUX

is below V

AUX(on)

or if V

AUX

reaches

7.0 V.

The outputs are biased directly from V

AUX

and their high

state voltage is approximately V

AUX

. Therefore, the

auxiliary supply voltage should not exceed the maximum

gate voltage of the main or active clamp MOSFET.

The high current drive capability of the outputs will

genera te inductance--induced spikes if inductance is not

reduce d on the outputs. This can be done by reducing the

connection length between the drivers and their loads and

using wide conne ctions.

Overlap Delay

The ove rlap delay prevents simultaneous conduction of

the main and active clamp MOSFETs. The secondary

output, OUT2, precedes OUT1 during a low to high

transition and trails OUT1 during a high to low transition.

Figure 47 shows the relationship between OUT1 and

OUT2.

(Leading)

OUT1

OUT2

(Trailing)

Figure 47. Output Timing Diagram

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The output overlap delay is adjusted by connecting a

resistor, R

, from the t

pin to ground. The overlap delay

is proportional to R

. A minimum delay of 20 ns is

obtained by grounding the t

pin.

The l eading delay is purposely made longer than the

trailing delay. This allows the user to optimize the delay for

the turn on transition of the main switch and ensures the

active clamp switch always e xhibits zero volt switching.

Analog and Power Ground (PGND)

The NCP1562 has an analog ground, GND, and a power

ground, PGND, terminal. GND is used for analog

connections such as V

REF

, feedforward among

others. PGND is used for high c urrent connecti ons such as

the internal output drivers. It is recommended to have

indepe ndent analog and power ground planes and connect

them at a single point, preferably at the ground terminal of

the system. This will prevent high current flowing on

PGND from injecting noise in GND. The PGND

connec tion should be as short and wide as possible to

reduce inductance--induced spikes.

Oscillator

The oscillator frequency and maximum duty cycle are

setbyanR

divider from V

REF

as shown in Figure 48.

A 500 mA current source (I

RTCT

) discharges the timing

capacitor (C

) upon reaching its peak threshold

RTCT(peak)

), typically 3.0 V. Once C

reaches its valley

voltage (V

RTCT(valley)

), typically 2.0 V, I

RTCT

turns OFF

allowing C

to charge back up through R

. The resulting

waveform on the RTCT pin has a sawtooth like shape.

Enable

RTCT

REF

RTCT

Figure 48. Oscillator Configuration

OUT2 is set high once V

RTCT(valley)

is reached, followed

by OUT1 delayed by the overlap delay. Once V

RTCT(peak)

is reached, OUT1 goes low, followed by OUT2 delayed by

The duty cycle is the C

charge time (t

RTCT(C)

) minus the

overla p delay over the total charge and discharge (t

RTCT(D)

)

times. The charge and discharge times are calculated using

Equations 5 and 6. However, these equations are an

approximation as they do not take into account the

propagation delays of the internal comparator.

RTCT(C)

= R

× ln



RTCT(valley)

-- V

REF

RTCT(peak)

-- V

REF



(eq. 5)

RTCT(D)

= R

× ln



RTCT

× R

) + V

RTCT(peak)

-- V

REF

RTCT

× R

) + V

RTCT(valley)

-- V

REF



(eq. 6)

The duty cycle , D, is given by Equation 7.

D =

RTCT(C)

-- t

RTCT(C)

+ t

RTCT(D)

(eq. 7)

Substituting Equations 5, 6, and 7, and after a little

algebraic manipulation and replacing values, it simplifies

to:

D =



RTCT(valley)

-- V

REF

RTCT(peak)

-- V

REF





RTCT(valley)

-- V

REF

RTCT(peak)

-- V

REF

RTCT

×R

)+V

RTCT(peak)

-- V

REF

RTCT

×R

)+V

RTCT(valley)

-- V

REF



(eq. 8)

It can be observed that D is set by R

and t

. This

equation has two variables and can be solved iteratively. In

general, the time delay isa small portionof the ON time and

can be ignored as a fir st approxi mation. R

is then selected

to achieve a gi ven duty cycle. Once the R

is selected, C

is chosen to obtain the desired operating frequency using

Equation 9.

f =

× ln



RTCT(valley)

-- V

REF

RTCT(peak)

-- V

REF

RTCT

×R

)+V

RTCT(peak)

-- V

REF

RTCT

×R

)+V

RTCT(valley)

-- V

REF



(eq. 9)

Figures 23 through 26 show the frequency and duty cycle

variation vs R

for several C

value s. R

should not be less

than 6.0 kΩ. Otherwise, the R

charge current will

exceed the pulldown current and the oscillator will be in an

undefined state.

Synchronization

A proprieta ry bidirec tional frequency synchronizat ion

architecture allows multiple NCP1562 to synchronize in a

master--slave configuration. It can synchronize to

frequenc ies above or below the free running frequency.

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NCP1562ADR2G

Mfr. #:

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