M48Z128, M48Z128Y Operating modes
Doc ID 2426 Rev 6 7/20
2 Operating modes
The M48Z128/Y also has its own power-fail detect circuit. The control circuitry constantly
monitors the single V
CC
supply for an out of tolerance condition. When V
CC
is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
CC
. As V
CC
falls below the
switchover voltage (V
SO
), the control circuitry connects the battery which maintains data
until valid power returns.
Table 2. Operating modes
Note: X = V
IH
or V
IL
; V
SO
= battery backup switchover voltage.
2.1 READ mode
The M48Z128/Y is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
1,048,576 locations in the static storage array. Thus, the unique address specified by the 17
address inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (t
AVQV
) after the last
address input signal is stable, providing that the E
and G (output enable) access times are
also satisfied. If the E
and G access times are not met, valid data will be available after the
later of chip enable access time (t
ELQV
) or output enable access time (t
GLQV
). The state of
the eight three-state data I/O signals is controlled by E
and G. If the outputs are activated
before t
AVQV
, the data lines will be driven to an indeterminate state until t
AVQV
. If the address
inputs are changed while E
and G remain low, output data will remain valid for output data
hold time (t
AXQX
) but will go indeterminate until the next address access.
Mode V
CC
E G W DQ0-DQ7 Power
Deselect
4.75 to 5.5 V
or
4.5 to 5.5 V
V
IH
X X High Z Standby
WRITE V
IL
XV
IL
D
IN
Active
READ V
IL
V
IL
V
IH
D
OUT
Active
READ V
IL
V
IH
V
IH
High Z Active
Deselect V
SO
to V
PFD
(min)
(1)
1. See Table 10 on page 15 for details.
X X X High Z CMOS standby
Deselect V
SO
(1)
X X X High Z Battery backup mode
Obsolete Product(s) - Obsolete Product(s)
Operating modes M48Z128, M48Z128Y
8/20 Doc ID 2426 Rev 6
Figure 4. Chip enable or output enable controlled, READ mode AC waveforms
Note: WRITE enable (W
) = high.
Figure 5. Address controlled, READ mode AC waveforms
Note: Chip enable (E
) and output enable (G) = low, WRITE enable (W) = high.
AI01197
tAVAV
tAVQV
tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
DATA OUT
A0-A16
E
G
DQ0-DQ7
VALID
AI01078
tAVAV
tAVQV tAXQX
A0-A16
DQ0-DQ7
VALID
DATA VALID
Table 3. READ mode AC characteristics
Symbol Parameter
(1)
1. Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
M48Z128/Y M48Z128/Y M48Z128/Y
Unit–70 –85 –120
Min Max Min Max Min Max
t
AVAV
READ cycle time 70 85 120 ns
t
AVQV
Address valid to output valid 70 85 120 ns
t
ELQV
Chip enable low to output valid 70 85 120 ns
t
GLQV
Output enable low to output valid 354560ns
t
ELQX
(2)
2. C
L
= 5 pF.
Chip enable low to output transition 5 5 5 ns
t
GLQX
(2)
Output enable low to output
transition
33 3ns
t
EHQZ
(2)
Chip enable high to output Hi-Z 30 3545ns
t
GHQZ
(2)
Output enable high to output Hi-Z 20 25 35ns
t
AXQX
Address transition to output
transition
5 5 10 ns
Obsolete Product(s) - Obsolete Product(s)
M48Z128, M48Z128Y Operating modes
Doc ID 2426 Rev 6 9/20
2.2 WRITE mode
The M48Z128/Y is in the WRITE mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W
or E. A WRITE is terminated by the
earlier rising edge of W
or E.
The addresses must be held valid throughout the cycle. E
or W must return high for
minimum of t
EHAX
from E or t
WHAX
from W prior to the initiation of another READ or WRITE
cycle. Data-in must be valid t
DVWH
prior to the end of WRITE and remain valid for t
WHDX
or
t
EHDX
afterward. G should be kept high during WRITE cycles to avoid bus contention;
although, if the output bus has been activated by a low on E
and G, a low on W will disable
the outputs t
WLQZ
after W falls.
Figure 6. WRITE enable controlled, WRITE AC waveforms
Note: Output enable (G
) = high.
Figure 7. Chip enable controlled, WRITE AC waveforms
Note: Output enable (G
) = high.
AI01198
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A16
E
W
DQ0-DQ7
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
AI01199
tAVAV
tEHAX
tDVEH
A0-A16
E
W
DQ0-DQ7
VALID
tAVEH
tAVEL
tAVWL
tELEH
tEHDX
DATA INPUT
Obsolete Product(s) - Obsolete Product(s)

AT45DB081D-SSU-2.5

Mfr. #:
Manufacturer:
Adesto Technologies
Description:
IC FLASH 8M SPI 50MHZ 8SOIC
Lifecycle:
New from this manufacturer.
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