OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

8533AG-01LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Low Skew, 1-to-4
Differential-to-3.3V LVPECL Fanout Buffer
8533-01
Data Sheet
©2016 Integrated Device Technology, Inc Revision F January 19, 20161
BLOCK DIAGRAM PIN ASSIGNMENT
8533-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
GENERAL DESCRIPTION
The 8533-01 is a low skew, high performance 1-to-4
Differential-to-3.3V LVPECL Fanout Buffer. The 8533-
01 has two selectable clock inputs. The CLK, nCLK pair
can accept most standard differential input levels. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL
input levels. The clock enable is internally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin. Guaranteed
output and part-to-part skew characteristics make the 8533-01
ideal for those applications demanding well defi ned performance
and repeatability.
FEATURES
• Four differential 3.3V LVPECL outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.4ns (maximum)
• Additive phase jitter, RMS: 0.06ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package
• Industrial temperature information available upon request
8533-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision F January 19, 20162
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
Number Name Type Description
1V
EE
Power Negative supply pin.
2 CLK_EN Input Pullup
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high. LVC-
MOS / LVTTL interface levels.
3 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects differential PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
4 CLK Input Pulldown Non-inverting differential clock input.
5 nCLK Input Pullup Inverting differential clock input.
6 PCLK Input Pulldown Non-inverting differential LVPECL clock input.
7 nPCLK Input Pullup Inverting differential LVPECL clock input.
8, 9 nc Unused No connect.
10, 13, 18 V
CC
Power Positive supply pins.
11, 12 nQ3, Q3 Output Differential output pair. LVPECL interface levels.
14, 15 nQ2, Q2 Output Differential output pair. LVPECL interface levels.
16, 17 nQ1, Q1 Output Differential output pair. LVPECL interface levels.
19, 20 nQ0, Q0 Output Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8533-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision F January 19, 20163
TABLE 3A. CONTROL INPUT FUNCTION TABLE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs Outputs
Input to Output Mode Polarity
CLK or PCLK nCLK or nPCLK Q0:Q3 nQ0:nQ3
0 1 LOW HIGH Differential to Differential Non Inverting
1 0 HIGH LOW Differential to Differential Non Inverting
0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inverting
1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inverting
Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inverting
Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
FIGURE 1. CLK_EN TIMING DIAGRAM
Inputs Outputs
CLK_EN CLK_SEL Selected Source Q0:Q3 nQ0:nQ3
0 0 CLK, nCLK Disabled; LOW Disabled; HIGH
0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH
1 0 CLK, nCLK Enabled Enabled
1 1 PCLK, nPCLK Enabled Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described
in Table 3B.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

8533AG-01LF

Mfr. #:
Buy 8533AG-01LF
Manufacturer:
IDT
Description:
Clock Buffer 1-to-4 LVPECL Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet