74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 13 of 24
NXP Semiconductors
74HC299; 74HCT299
8-bit universal shift register; 3-state
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
pd
is the same as t
PHL
.
[3] t
t
is the same as t
THL
and t
TLH
.
[4] t
en
is the same as t
PZH
and t
PZL
.
[5] t
dis
is the same as t
PHZ
and t
PLZ
.
t
t
transition time bus driver (I/On); see Figure 7
[3]
V
CC
= 4.5 V - 5 12 - 15 - 18 ns
standard (Q0, Q7); see
Figure 7
V
CC
= 4.5 V - 7 15 - 19 - 22 ns
t
W
pulse width clock HIGH or LOW; see Figure 7
V
CC
= 4.5 V 20 10 - 25 - 30 - ns
master reset LOW; see
Figure 8
V
CC
= 4.5 V 20 11 - 25 - 30 - ns
t
en
enable time OEn to I/On; see Figure 10
[4]
V
CC
= 4.5 V - 19 30 - 38 - 45 ns
t
PHZ
HIGH to
OFF-state
propagation
delay
OEn to I/On; see Figure 10
[5]
V
CC
= 4.5 V - 24 37 - 46 - 56 ns
t
PLZ
LOW to
OFF-state
propagation
delay
OEn to I/On; see Figure 10
V
CC
= 4.5 V - 20 32 - 40 - 48 ns
t
rec
recovery time MR to CP; see Figure 8
V
CC
= 4.5 V 10 2 - 9 - 11 - ns
t
su
set-up time I/On, DSR, DSL to CP;
see
Figure 7
V
CC
= 4.5 V 25 14 - 31 - 38 - ns
S0, S1 to CP; see
Figure 9
V
CC
= 4.5 V 32 18 - 40 - 48 - ns
t
h
hold time I/On, DSR, DSL to CP;
see
Figure 7
V
CC
= 4.5 V 0 11-0-0-ns
S0, S1 to CP; see
Figure 9
V
CC
= 4.5 V 0 17-0-0-ns
f
max
maximum
frequency
CP input; see Figure 7
V
CC
= 4.5 V 25 42 - 20 - 17 - MHz
V
CC
= 5.0 V; C
L
= 15 pF -46-----MHz
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter Conditions 25 °C 40 °C to
+85 °C
40 °C to
+125 °C
Unit
Min Typ Max Min Max Min Max
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 14 of 24
NXP Semiconductors
74HC299; 74HCT299
8-bit universal shift register; 3-state
[6] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
= C
PD
× V
CC
2
× f
i
× N + Σ(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
Σ(C
L
× V
CC
2
× f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching.
11. Waveforms
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7. Clock pulse to outputs I/On, Q0, Q7 propagation delays, the clock pulse width, the I/On, DSR and DSL to
clock pulse set-up and hold times, the output transition times and the maximum clock frequency
001aai462
t
h
t
su
t
h
t
PHL
t
THL
t
TLH
t
W
t
PLH
t
su
1/f
max
V
M
V
M
V
M
CP input
V
I
GND
V
I
GND
V
OH
V
OL
I/On, DSR, DSL
inputs
I/On, Q0, Q7
outputs
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 15 of 24
NXP Semiconductors
74HC299; 74HCT299
8-bit universal shift register; 3-state
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8. The master reset pulse width (LOW), the master reset to outputs I/On, Q0, Q7 propagation delays and the
master reset to clock pulse removal time
001aai463
I/On, Q0, Q7
outputs
V
M
t
PHL
V
M
MR input
V
M
GND
GND
V
I
t
W
t
rec
CP input
V
OL
V
I
V
OH
Measurement points are given in Table 8.
Fig 9. Set-up and hold times from the mode control inputs S0, S1 to the clock pulse
001aai464
I/On, DSR, DSL, Sn
inputs
CP input
t
su
t
h
V
M
V
I
GND
GND
V
I
V
M
t
su
t
h

74HC299D,653

Mfr. #:
Manufacturer:
Nexperia
Description:
Counter Shift Registers 8-BIT UNIVERSAL SHFT REG 3-S
Lifecycle:
New from this manufacturer.
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