AT49BV1614-11TI Datasheet AT49BV1604-11UI, AT49BV1614-11TI, AT49BV1614-90TC | P4-P6

AT49BV1604(T)/1614(T)

The command sequences are written by applying a low

pulse on the WE

or CE input with CE or WE low (respec-

tively) and OE

high. The address is latched on the falling

edge of CE

or WE, whichever occurs last. The data is

latched by the first rising edge of CE

or WE. Standard

microprocessor write timings are used. The address loca-

tions used in the command sequences are not affected by

entering the command sequences.

RESET: A RESET

input pin is provided to ease some sys-

tem applications. When RESET

is at a logic high level, the

device is in its standard operating mode. A low level on the

RESET

input halts the present device operation and puts

the outputs of the device in a high-impedance state. When

a high level is reasserted on the RESET

pin, the device

returns to the read or standby mode, depending upon the

state of the control inputs. By applying a 12V

± 0.5V input

signal to the RESET

pin, any sector can be reprogrammed

even if the sector lockout feature has been enabled (see

Sector Programming Lockout Override section).

ERASURE: Before a byte/word can be reprogrammed, it

must be erased. The erased state of memory bits is a logi-

cal “1”. The entire device can be erased by using the Chip

Erase command or individual sectors can be erased by

using the Sector Erase command.

CHIP ERASE: The entire device can be erased at one time

by using the six-byte chip erase software code. After the

chip erase has been initiated, the device will internally time

the erase operation so that no external clocks are required.

The maximum time to erase the chip is t

If the sector lockout has been enabled, the chip erase will

not erase the data in the sector that has been locked; it will

erase only the unprotected sectors. After the chip erase,

the device will return to the read or standby mode.

SECTOR ERASE: As an alternative to a full chip erase, the

device is organized into 40 sectors (SA0 - SA39) that can

be individually erased. The Sector Erase command is a six-

bus cycle operation. The sector address is latched on the

falling WE

edge of the sixth cycle while the 30H data input

command is latched on the rising edge of WE

. The sector

erase starts after the rising edge of WE

of the sixth cycle.

The erase operation is internally controlled; it will automati-

cally time to completion. The maximum time to erase a

section is t

SEC

. When the sector programming lockout fea-

ture is not enabled, the sector will erase (from the same

Sector Erase command). Once a sector has been pro-

tected, data in the protected sectors cannot be changed

unless the RESET

pin is taken to 12V ± 0.5V. An attempt to

erase a sector that has been protected will result in the

operation terminating in 2 µs.

BYTE/WORD PROGRAMMING: Once a memory block is

erased, it is programmed (to a logical “0”) on a byte-by-byte

or on a word-by-word basis. Programming is accomplished

via the internal device command register and is a four-bus

cycle operation. The device will automatically generate the

required internal program pulses.

Any commands written to the chip during the embedded

programming cycle will be ignored. If a hardware reset hap-

pens during programming, the data at the location being

programmed will be corrupted. Please note that a data “0”

cannot be programmed back to a “1”; only erase operations

can convert “0”s to “1”s. Programming is completed after

the specified t

cycle time. The Data Polling feature or the

Toggle Bit feature may be used to indicate the end of a pro-

gram cycle.

SECTOR PROGRAMMING LOCKOUT: Each sector has a

programming lockout feature. This feature prevents pro-

gramming of data in the designated sectors once the

feature has been enabled. These sectors can contain

secure code that is used to bring up the system. Enabling

the lockout feature will allow the boot code to stay in the

device while data in the rest of the device is updated. This

feature does not have to be activated; any sector’s usage

as a write-protected region is optional to the user.

Once the feature is enabled, the data in the protected sec-

tors can no longer be erased or programmed when input

levels of 5.5V or less are used. Data in the remaining sec-

tors can still be changed through the regular programming

method. To activate the lockout feature, a series of six pro-

gram commands to specific addresses with specific data

must be performed. Please refer to the Command Defini-

tions table.

SECTOR LOCKOUT DETECTION: A software method is

available to determine if programming of a sector is locked

out. When the device is in the software product identifica-

tion mode (see Software Product Identification Entry and

Exit sections) a read from address location 00002H within a

sector will show if programming the sector is locked out. If

the data on I/O0 is low, the sector can be programmed; if

the data on I/O0 is high, the program lockout feature has

been enabled and the sector cannot be programmed. The

software product identification exit code should be used to

return to standard operation.

SECTOR PROGRAMMING LOCKOUT OVERRIDE: The

user can override the sector programming lockout by taking

the RESET

pin to 12V ± 0.5V. By doing this, protected data

can be altered through a chip erase, sector erase or

byte/word programming. When the RESET

pin is brought

back to TTL levels, the sector programming lockout feature

is again active.

ERASE SUSPEND/ERASE RESUME: The Erase Sus-

pend command allows the system to interrupt a sector

erase operation and then program or read data from a dif-

ferent sector within the same plane. Since this device has a

dual-plane architecture, there is no need to use the Erase

AT49BV1604(T)/1614(T)

Suspend feature while erasing a sector when you want to

read data from a sector in the other plane. After the Erase

Suspend command is given, the device requires a maxi-

mum time of 15 µs to suspend the erase operation. After

the erase operation has been suspended, the plane that

contains the suspended sector enters the erase-suspend-

read mode. The system can then read data or program

data to any other sector within the device. An address is

not required during the Erase Suspend command. During a

sector erase suspend, another sector cannot be erased. To

resume the sector erase operation, the system must write

the Erase Resume command. The Erase Resume com-

mand is a one-bus cycle command, which does require the

plane address (determined by A18 and A19). The device

also supports an erase suspend during a complete chip

erase. While the chip erase is suspended, the user can

read from any sector within the memory that is protected.

The command sequence for a chip erase suspend and a

sector erase suspend are the same.

PRODUCT IDENTIFICATION: The product identification

mode identifies the device and manufacturer as Atmel. It

may be accessed by hardware or software operation. The

hardware operation mode can be used by an external pro-

grammer to identify the correct programming algorithm for

the Atmel product.

For details, see “Operating Modes” on page 9 (for hard-

ware operation) or “Software Product Identification

Entry/Exit” on page 14. The manufacturer and device code

is the same for both modes.

DATA

POLLING: The AT49BV16X4(T) features Data Poll-

ing to indicate the end of a program cycle. During a

program cycle an attempted read of the last byte/word

loaded will result in the complement of the loaded data on

I/O7. Once the program cycle has been completed, true

data is valid on all outputs and the next cycle may begin.

During a chip or sector erase operation, an attempt to read

the device will give a “0” on I/O7. Once the program or

erase cycle has completed, true data will be read from the

device. Data

Polling may begin at any time during the pro-

gram cycle. Please see “Status Bit Table” on page 15 for

more details.

TOGGLE BIT: In addition to Data

Polling, the

AT49BV16X4(T) provides another method for determining

the end of a program or erase cycle. During a program or

erase operation, successive attempts to read data from the

same memory plane will result in I/O6 toggling between

one and zero. Once the program cycle has completed, I/O6

will stop toggling and valid data will be read. Examining the

toggle bit may begin at any time during a program cycle.

An additional toggle bit is available on I/O2, which can be

used in conjunction with the toggle bit that is available on

I/O6. While a sector is erase suspended, a read or a pro-

gram operation from the suspended sector will result in the

I/O2 bit toggling. Please see “Status Bit Table” on page 15

for more details.

RDY/BUSY

: An open drain Ready/Busy output pin pro-

vides another method of detecting the end of a program or

erase operation. RDY/BUSY

is actively pulled low during

the internal program and erase cycles and is released at

the completion of the cycle. The open drain connection

allows for OR-tying of several devices to the same

RDY/BUSY

line.

HARDWARE DATA PROTECTION: The Hardware Data

Protection feature protects against inadvertent programs to

the AT49BV16X4(T) in the following ways: (a) V

sense: if

is below 1.8V (typical), the program function is inhib-

ited. (b) V

power-on delay: once V

has reached the

sense level, the device will automatically time out

10 ms (typical) before programming. (c) Program inhibit:

holding any one of OE

low, CE high or WE high inhibits

program cycles. (d) Noise filter: pulses of less than 15 ns

(typical) on the WE

or CE inputs will not initiate a program

cycle.

INPUT LEVELS: While operating with a 2.7V to 3.6V

power supply, the address inputs and control inputs (OE

and WE) may be driven from 0 to 5.5V without

adversely affecting the operation of the device. The I/O

lines can only be driven from 0 to V

+ 0.6V.

OUTPUT LEVELS: For the 49BV1604(T), output high

levels (V

) are equal to V

CCQ

- 0.2V (not V

). For 2.7V -

3.6V output levels, V

CCQ

must be tied to V

. For 1.8V -

2.2V output levels, V

CCQ

must be regulated to 2.0V ± 10%,

while V

must be regulated to 2.7V - 3.0V (for minimum

power).

AT49BV1604(T)/1614(T)

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).

The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, A14 - A19 (Don’t Care).

2. Either one of the Product ID Exit commands can be used.

3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see next two

pages for details).

4. When the sector programming lockout feature is not enabled, the sector will erase (from the same Sector Erase command).

Once the sector has been protected, data in the protected sectors cannot be changed unless the RESET

pin is taken to

12V ± 0.5V.

5. PA is the plane address (A19 - A18).

Command Definition in Hex

(1)

Command

Sequence

Bus

Cycles

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read 1 Addr D

OUT

Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA

(3)(4)

Byte/Word Program 4 5555 AA 2AAA 55 5555 A0 Addr D

Bypass Unlock 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 A0

Single Pulse

Byte/Word Program

1 Addr D

Sector Lockout 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA

(3)(4)

Erase Suspend 1 xxxx B0

Erase Resume 1 PA

(5)

Product ID Entry 3 5555 AA 2AAA 55 5555 90

Product ID Exit

(2)

3 5555 AA 2AAA 55 5555 F0

Product ID Exit

(2)

1 xxxx F0

Absolute Maximum Ratings*

Temperature under Bias ................................ -55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Storage Temperature ..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

+ 0.6V

Voltage on OE

with Respect to Ground ...................................-0.6V to +13.5V

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

AT49BV1614-11TI

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