PCA9534 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 4 — 7 November 2017 5 of 27
NXP Semiconductors
PCA9534
8-bit I
2
C-bus and SMBus low power I/O port with interrupt
[1] HVQFN package die supply ground is connected to both V
SS
pin and exposed center pad. V
SS
pin must be
connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level
performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the
board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in
the thermal pad region.
6. Functional description
Refer to Figure 1 “Block diagram of PCA9534”.
6.1 Registers
6.1.1 Command byte
The command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the following registers will be written or read.
6.1.2 Register 0 - Input Port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by Register 3. Writes to this register
have no effect.
The default ‘X’ is determined by the externally applied logic level.
IO6 11 9 input/output 6
IO7 12 10 input/output 7
INT
13 11 interrupt output (open-drain)
SCL 14 12 serial clock line
SDA 15 13 serial data line
V
DD
16 14 supply voltage
Table 3. Pin description
…continued
Symbol Pin Description
SO16, TSSOP16 HVQFN16
Table 4. Command byte
Command Protocol Function
0 read byte Input Port register
1 read/write byte Output Port register
2 read/write byte Polarity Inversion register
3 read/write byte Configuration register
