MP86961 –20A, 27V INTELLI-PHASE
SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
MP86961 Rev. 1.22 www.MonolithicPower.com 9
12/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
OPERATION
The MP86961 is a 20A Monolithic Half Bridge
driver with MOSFETs ideally suited for single-
/multi-phase Buck regulators.
Once the EN, V
IN
, V
CC
and V
BST
signals are
sufficiently high, operation begins. BST voltage
has a typical rising UVLO of 2.2V and a falling
UVLO of 2.0V. When BST is below the UVLO
voltage, the device will be off.
MP86961 can work with most PWM controllers.
The device accepts PWM signal from 100kHz up
to 1MHz. There is an internal resistor divider to
put PWM voltage to tri-state region if the PWM
pin is open.
Internally, SYNC is tied to V
CC
through a resistor.
By default, the device will operate in synchronous
mode. To enter Diode Emulation mode, drive
SYNC pin LOW.
Startup and Shutdown Sequence
MP86961 can work with any startup or shutdown
sequencing combination of V
IN
, V
CC
and EN. If
PWM signal is present, the MP86961 will start
working whenever V
IN
, V
CC
and EN are ready.
On the other hand, if any of these signals is not
ready, the MP86961 will stop working. However,
it is recommended to turn on and turn off the
device through the EN pin.
PCB Layout Guideline
PCB layout is very important to achieve stable
operation. Please follow these guidelines to
achieve optimal performance.
1) Keep the path of switching current short and
minimize the loop area formed by input capacitor.
Keep the connection between SW pin and input
power ground as short and wide as possible.
2) Always place some input bypass ceramic
capacitors next to the device and on the same
layer as the device. Do not put all of the input
bypass capacitors on the back side of the device.
Use as many vias and input voltage planes as
possible to reduce the switching spike. BST
capacitor and V
CC
capacitor should also be as
close to the device as possible.
3) The recommended external BST cap is 100nF.
Do not use a capacitance value lower than
100nF. Place a 1.0Ω resistor between the BST
capacitor and BST pin for optimized performance.
4) Do not place via on the pad or on the pin
footprint. Doing so may cause soldering issue
during the assembling process. Use Figure 3 as
a via placement reference.
5) Connect IN, SW and GND to large copper
area and use vias to cool the chip to improve
thermal performance and long-term reliability.
See Figure 4 as an example.
Figure 3—Via Placement Guideline
Do not put via on the device’s pad footprint or pin
footprint to avoid assembly issue. Use as many
vias as possible to cool down the device.
6) Place the V
CC
decouple capacitor close to the
IC. Connect AGND and PGND at the point of
V
CC
capacitor's ground connection.
Recommended SMT Setting
Stencil thickness: 0.12mm
EP Pad Opening: (Stencil opening : Real PCB
Size)
Length: 0.85:1
Width: 1:1
Note: The EP pad for Intelli-Phase are IN,
SW and GND pad on the bottom.
Solder type: #3
