AD9741/AD9743/AD9745/AD9746/AD9747 Data Sheet
Rev. A | Page 25 of 28
0
–10
–20
–30
–40
T(f) (dB)
0.5 1.5 2
F
S
NORMAL
RZ
MIX
06569-027
Figure 36. Transfer Function for Each Analog Operating Mode
AUXILIARY DACS
Two auxiliary DACs are provided on the AD9741/AD9743/
AD9745/AD9746/AD9747. A functional diagram is shown
in Figure 37. The auxiliary DACs are current output devices
with two output pins, AUXP and AUXN. The active pin can
be programmed to either source or sink current. When either
sinking or sourcing, the full-scale current magnitude is 2 mA.
The available compliance range at the auxiliary DAC outputs
depends on whether the output is configured to a sink or source
current. When sourcing current, the compliance voltage is 0 V
to 1.6 V, but when sinking current, the output compliance
voltage reduces to 0.8 V to 1.6 V. Either output can be used, but
only one output of the auxiliary DAC (P or N) is active at any
time. The inactive pin is always in a high impedance state
(>100).
06569-035
V
BIAS
AUXP
AUXN
SINK
OR
SOURCE
POSITIVE
OR
NEGATIVE
0mA
TO
2mA
0mA
TO
2mA
Figure 37. Auxiliary DAC Functional Diagram
In a single side band transmitter application, the combination of
the input referred dc offset voltage of the quadrature modulator
and the DAC output offset voltage can result in local oscillator
(LO) feedthrough at the modulator output, which degrades
system performance. The auxiliary DACs can be used to remove
the dc offset and the resulting LO feedthrough. The circuit
configuration for using the auxiliary DACs for performing
dc offset correction depends on the details of the DAC and
modulator interface. An example of a dc-coupled configuration
with low-pass filtering is outlined in the Power Dissipation
section.
AD9747
AUX
DAC1 OR
DAC2
AD9747
DAC1 OR
DAC2
25Ω TO 50Ω
QUAD MOD
I OR Q INPUTS
QUADRATURE
MODULATOR V+
25Ω TO 50Ω
06569-029
OPTIONAL
PASSIVE
FILTERING
Figure 38. DAC DC Coupled to Quadrature Modulator with Passive DC Shift
POWER DISSIPATION
Figure 39 shows the power dissipation and current draw of the
AD9741/AD9743/AD9745/AD9746/AD9747. It shows that the
devices have a quiescent power dissipation of about 190 mW.
Most of this comes from the AVDD33 supply. Total power
dissipation increases about 50% as the clock rate is increased
to the maximum clock rate of 250 MHz.
350
310
270
230
190
150
P
TOTAL
(mW)
0
50
100
150
200 250
f
DAC
(MHz)
06569-030
25
75
125 175
225
f
OUT
= DC
f
OUT
= NYQUIST
Figure 39. AD9747 Power Dissipation vs. f
DAC
15
12
9
6
3
0
I
DVDD33
(mA)
0 50
100 150
200 250
f
DAC
(MHz)
06569-031
25 75
125 175
225
AD9747
AD9741
Figure 40. DVDD33 Current vs. f
DAC
AD9741/AD9743/AD9745/AD9746/AD9747 Data Sheet
Rev. A | Page 26 of 28
30
24
18
12
6
0
I
DVDD18
(mA)
0
50
100
150
200
250
f
DAC
(MHz)
06569-032
25
75
125
175
225
AD9747
AD9741
Figure 41. DVDD18 Current vs. f
DAC
15
13
11
9
7
5
I
CVDD18
(mA)
0 50 100 150 200 250
f
DAC
(MHz)
06569-033
25 75 125 175 225
Figure 42. CVDD18 Current vs. f
DAC
Figure 43 shows the power consumption for each power supply
domain as well as the total power consumption. Individual bars
within each group display the power in full active mode (blue)
vs. power for five increasing levels of power-down.
06569-045
P
DISS
(mW)
0
50
100
150
200
250
300
350
AVDD33 DVDD18
CVDD18 DVDD33 TOT PWR
FULL ACTIVE
DCO OFF
AUX OFF
D
AC
OFF
CLK OFF
BIAS OFF
Figure 43. Power Dissipation vs. Power-Down Mode
The overall power consumption is dominated by AVDD33 and
significant power savings can be achieved simply by disabling
the DAC outputs. Also, disabling the DAC outputs is a signifi-
cant way to conserve power and still maintain a fast wake-up
time. Full power-down disables all circuitry for minimum
power consumption. Note, however, that even in full power-
down, there is a small power draw (25 mW) due to incoming
data activity. To lower power consumption to near zero, all
incoming data activity must be halted.
Data Sheet AD9741/AD9743/AD9745/AD9746/AD9747
Rev. A | Page 27 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4
0.20 REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
0.05 MAX
0.02 NOM
1
18
54
37
19
36
72
55
0.50
0.40
0.30
8.50 REF
4.70
BSC SQ
PIN 1
INDICATOR
SEATING
PLANE
12° MAX
0.60
0.42
0.24
0.60
0.42
0.24
0.30
0.23
0.18
0.50
BSC
PIN 1
INDICATOR
COPLANARITY
0.08
06-15-2012-A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
TOP VIEW
EXPOSED
PAD
BOTTOM VIEW
10.10
10.00 SQ
9.90
9.85
9.75 SQ
9.65
0.25 MIN
Figure 44. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
10 mm × 10 mm, Very Thin Quad
(CP-72-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option
AD9741BCPZ
−40°C to +85°C
72-Lead LFCSP_VQ
CP-72-1
AD9741BCPZRL 40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9743BCPZ −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9743BCPZRL
−40°C to +85°C
72-Lead LFCSP_VQ
CP-72-1
AD9745BCPZ −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9745BCPZRL 40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9746BCPZ −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9746BCPZRL 40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9747BCPZ −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9747BCPZRL 40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9741-DPG2-EBZ Evaluation Board
AD9743-DPG2-EBZ Evaluation Board
AD9745-DPG2-EBZ Evaluation Board
AD9746-DPG2-EBZ Evaluation Board
AD9747-DPG2-EBZ
Evaluation Board
1
Z = RoHS Compliant Part.

AD9746BCPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Dual 14-Bit 250 MSPS
Lifecycle:
New from this manufacturer.
Delivery:
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