AD9741/AD9743/AD9745/AD9746/AD9747 Data Sheet
Rev. A | Page 12 of 28
1
2
3
4
5
6
7
8
9
10
1
1
12
13
14
15
16
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
P1D13
P1D12
P1D
1
1
P1D10
P1D9
P1D8
P1D7
P1D6
17P1D5
18P1D4
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
P1D3
P1D2
P1D1
P1D0
NC
NC
DCO
NC
DVDD33
DVSS
IQSE
L
NC
P2D13
P2D12
P2D11
P2D10
35
P2D9
36
P2D8
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
FSADJ
RESET
CSB
SCLK
SDIO
SDO
DVSS
DVDD18
NC
NC
P2D0
P2D1
P2D2
P2D3
P2D4
P2D5
P2D6
P2D7
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD33
AVDD33
AVSS
IOUT1P
IOUT1N
AVSS
AUX1P
AUX1N
A
VSS
AUX2N
AUX2P
AVSS
IOUT2N
IOUT2P
AVSS
A
VDD33
AVDD33
REFIO
NC = NO CONNECT
06569-003
PIN 1
INDIC
A
TOR
AD9746
(
TO
P
VIEW)
Figure 5. AD9746 Pin Configuration
Table 11. AD9746 Pin Function Descriptions
Pin No. Mnemonic Description
1, 6 CVDD18 Clock Supply Voltage (1.8 V).
2, 5 CVSS Clock Supply Common (0 V).
Differential DAC Clock Input.
4 CLKN Complementary Differential DAC Clock Input.
7, 28, 48 DVSS Digital Supply Common (0 V).
8, 47 DVDD18 Digital Core Supply Voltage (1.8 V).
9 to 22 P1D<13:0> Port 1 Data Bit Inputs.
23, 24, 26, 30, 45, 46 NC No Connect.
Data Clock Output. Use to clock data source.
27 DVDD33 Digital I/O Supply Voltage (3.3 V).
29 IQSEL I/Q Framing Signal for Single-Port Mode Operation.
31 to 44 P2D<13:0> Port 2 Data Bit Inputs.
49 SDO Serial Peripheral Interface Data Output.
50 SDIO Serial Peripheral Interface Data Input and Optional Data Output.
51 SCLK Serial Peripheral Interface Clock Input.
52 CSB Serial Peripheral Interface Chip Select Input. Active low.
53 RESET Hardware Reset. Active high.
54 FSADJ Full-Scale Current Output Adjust. Connect a 10 kΩ resistor to AVSS.
55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS.
Analog Supply Voltage (3.3 V).
58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V).
59 IOUT2P DAC2 Current Output True. Sources full-scale current when input data bits are all 1.
60 IOUT2N DAC2 Current Output Complement. Sources full-scale current when data bits are all 0.
62 AUX2P Auxiliary DAC2 Default Current Output Pin.
63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI.
Auxiliary DAC1 Optional Output Pin. Enable through SPI.
66 AUX1P Auxiliary DAC1 Default Current Output Pin.
68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0.
69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1.
EPAD AVSS
Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability
and must be electrically tied to low impedance GND plane for low noise performance.
