M2040-01-533.3334T Datasheet M2040-01-533.3334T, M2040-01-533.3334 | P4-P6

M2040 Datasheet Rev 1.0 4 of 12 Revised 28Jan2005

Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400

Integrated

Circuit

Systems, Inc.

M2040

REQUENCY

RANSLATION

PLL

WITH

UTO

WITCH

Product Data Sheet

FUNCTIONAL DESCRIPTION

The M2040 is a PLL (Phase Locked Loop) based clock

generator that generates two output clocks

synchronized to one of two selectable input reference

clocks. An internal high “Q” SAW delay line provides a

low jitter clock output.

The device is pin-configured for feedback divider and

output divider values. Output is LVPECL compatible.

External loop filter component values set the PLL

bandwidth to optimize jitter attenuation characteristics.

The device features dual differential inputs with two

input selection modes: manual and automatic upon

clock failure. (The differential inputs are internally

configured for easy single-ended operation.)

The M2040 includes: a Loss of Lock (

LOL) indicator, a

reference mux state acknowledge pin (

REF_ACK), a

Narrow Bandwidth control input pin (

NBW pin), and a

Power-on Initialization (

INIT) input (which overrides

NBW=0 to facilitate acquisition of phase lock).

Hitless Switching (HS) is an optional feature that

provides a controlled output clock phase change during

a reference clock reselection. HS is triggered by a Loss

of Lock detection by the PLL.

Input Reference Clocks

Two clock reference inputs and a selection mux are

provided. Either reference clock input can accept a

differential clock signal (such as LVPECL or LVDS) or

a single-ended clock input (LVCMOS or LVTTL on the

non-inverting input).

A single-ended reference clock on the unselected

reference input can cause an increase in output

clock jitter. For this reason, differential reference

inputs are preferred; interference from a differential

input on the non-selected input is minimal.

Configuration of a single-ended input has been

facilitated by biasing

nDIF_REF0 and nDEF_REF1 to Vcc/2,

with 50kΩ to Vcc and 50kΩ to ground. The input clock

structure, and how it is used with either

LVCMOS/LVTTL inputs or a DC- coupled LVPECL

clock, is shown in Figure 4.

Figure 4: Input Reference Clocks

Differential Inputs

Differential LVPECL inputs are connected to both

reference input pins in the usual manner. The external

load termination resistors shown in Figure 4 (the

127Ω

and

82Ω resistors) is ideally suited for both AC and DC

coupled LVPECL reference clock lines. These provide

the

50Ω load termination and the VTT bias voltage.

Single-ended Inputs

Single-ended inputs (LVCMOS or LVTTL) are

connected to the non-inverting reference input pin

(

DIF_REF0 or DIF_REF1). The inverting reference input pin

(

nDIF_REF0 or nDIF_REF1) must be left unconnected.

In single-ended operation, when the unused inverting

input pin (nDIF_REF0 or nDEF_REF1) is left floating (not

connected), the input will self-bias at VCC/2.

MUX

REF_SEL

VCC

50k

VCC

50k

LVCMOS/

LVTTL

LVPECL

50k

VCC

127

VCC

127

DIF_REF0

nDIF_REF0

DIF_REF1

nDIF_REF1

Ω

M2040 Datasheet Rev 1.0 5 of 12 Revised 28Jan2005

Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400

M2040

REQUENCY

RANSLATION

PLL

WITH

UTO

WITCH

Product Data Sheet

Integrated

Circuit

Systems, Inc.

PLL Operation

The M2040 is a complete clock PLL. It uses a phase

detector and configurable dividers to synchronize the

output of the VCSO with the selected reference clock.

The “M” divider (and the “Mfin” divider) divides the

VCSO output frequency, feeding the result into the plus

input of the phase detector.

The frequency input (“Mfin”) divider gives the device

the capability to be adapted for use with other input

frequencies.

The output of the “R” divider is fed into the minus input

of the phase detector. The phase detector compares its

two inputs. The phase detector output, filtered

externally, causes the VCSO to increase or decrease in

frequency as needed to phase- and frequency-lock the

VCSO to the reference input.

The value of M plus Mfin directly affects closed loop

bandwidth.

The relationship between the nominal VCSO center

frequency (Fvcso), the M divider, and the input

reference frequency (Fref_clk) is:

The M, R, and Mfin dividers can be set by pin

configuration using

the input pins MR_SEL, FIN_SEL1, and

FIN_SEL0.

P Divider and Outputs

The M2040 provides two differential LVPECL output

pairs:

FOUT0 and FOUT1. One output divider (the “P”

divider) is used for both the

FOUT0 and FOUT1 output

pairs. By using the P divider, the output frequency can

be the VCSO frequency (Fvcso) or 1/2 Fvcso.

The

P_SEL pin selects the value for the P divider: logic 1

sets P to divide-by-

2, logic 0 sets P to divide-by-1.

See Table 5, P Divider Selector Values

and Frequencies, on pg. 3.

When the P divider is included, the complete relation-

ship for the output frequency (Fout) is defined as:

Loss of Lock Indicator Output Pin

Under normal device operation, when the PLL is locked,

LOL remains at logic 0. Under circumstances when the

VCSO cannot lock to the input (as measured by a

greater than 4 ns discrepancy between the feedback

and reference clock rising edges at the phase detector)

the

LOL output goes to logic 1. The LOL pin will return

back to logic

0 when the phase detector error is less

than 2 ns. The loss of lock indicator is a low current

CMOS output.

Narrow Loop Bandwidth Control Pin (NBW Pin)

A Narrow Loop Bandwidth control pin (

NBW pin) is

included to adjust the PLL loop bandwidth. In normal

(wide) bandwidth mode (

NBW=0), the internal resistor

Rin is 100kΩ

. With the NBW pin asserted, the internal

resistor Rin is changed to 2100kΩ

. This lowers the loop

bandwidth by a factor of about 21 (2100 / 100) and

lowers the damping factor by about 4.6 (the square root

of 21), assuming the same loop filter components.

Fvcso Fref_clk

MMfin×

--------------------------

×=

Fout

Fvcso

-------------------

= Fref_clk

MMfin×

RP×

--------------------------

×=

M2040 Datasheet Rev 1.0 6 of 12 Revised 28Jan2005

Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400

Integrated

Circuit

Systems, Inc.

M2040

REQUENCY

RANSLATION

PLL

WITH

UTO

WITCH

Product Data Sheet

Automatic Reference Clock Reselection

This device offers an automatic reference clock

reselection feature for switching input reference clocks

upon a reference clock failure. With the

AUTO input pin

set to high and the

LOL output low, the device is placed

into automatic reselection (AutoSwitch) mode.

Once in AutoSwitch mode, when

LOL then goes high

(due to a reference clock fault), the input clock

reference is automatically reselected internally, as

indicated by the state change of the

REF_ACK output.

Automatic clock reselection is made only once (it is

non-revertive). Re-arming of automatic mode requires

placing the device into manual selection (Manual

Select) mode (

AUTO pin low) before returning to

AutoSwitch mode (

AUTO pin high).

Using the AutoSwitch Feature

See also Table 6, Example AutoSwitch Sequence.

In application, the system is powered up with the device

in Manual Select mode (

AUTO pin is set low), allowing

sufficient time for the reference clock and device PLL to

settle. The

REF_SEL input selects the reference clock to

be used in Manual Select mode and the initial reference

clock used in AutoSwitch mode. The

REF_SEL input state

must be maintained when switching to AutoSwitch

mode (

AUTO pin high) and must still be maintained until a

reference fault occurs.

Once a reference fault occurs, the

LOL output goes high

and the input reference is automatically reselected. The

REF_ACK output always indicates the reference selection

status and the

LOL output always indicates the PLL lock

status.

A successful automatic reselection is indicated by a

change of state of the

REF_ACK output and a momentary

level high of the

LOL output (minimum high time is 10ns).

If an automatic reselection is made to a non-valid

reference clock (one to which the PLL cannot lock),

the REF_ACK output will change state but the LOL

output will remain high.

No further automatic reselection is made; only one

reselection is made each time the AutoSwitch mode is

armed. AutoSwitch mode is re-armed by placing the

device into Manual Select mode (

AUTO pin low) and then

into AutoSwitch mode again (

AUTO pin high).

Following an automatic reselection and prior to

selecting Manual Select mode (

AUTO pin low), the

REF_SEL pin has no control of reference selection.

To prevent an unintential reference reselection,

AutoSwitch mode must not be re-enabled until the

desired state of the

REF_SEL pin is set and the LOL output

is low. It is recommended to delay the re-arming of

AutoSwitch mode, following an automatic reselection, to

ensure the PLL is fully locked on the new reference. In

most system configurations, where loop bandwidth is in

the range of 100-1000 Hz and damping factor below 10,

a delay of 500 ms should be sufficient. Until the PLL is

fully locked intermittent LOL pulses may occur.

Example AutoSwitch Sequence

0 = Low; 1 = High. Example with

REF_SEL

initially set to 0 (i.e.,

DIF_REF0

selected)

REF_SEL

Selected

Clock Input

REF_ACK AUTO LOL Conditions

Input Output Input Output

Initialization

DIF_REF0

0 0 1

Device power-up. Manual Select mode. DIF_REF0 input selected reference, not yet locked to.

DIF_REF0

0 0 -0-

LOL to 0: Device locked to reference (may get intermittent LOL pulses until fully locked).

DIF_REF0

0 -1- 0

AUTO set to 1: Device placed in AutoSwitch mode (with DIF_REF0 as initial reference clock).

Operation & Activation

DIF_REF0

0 1 0

Normal operation with AutoSwitch mode armed, with DIF_REF0 as initial reference clock.

DIF_REF0

0 1 -1-

LOL to 1: Clock fault on DIF_REF0, loss of lock indicated by LOL pin, ...

-DIF_REF1-

-1- 1 1

... and immediate automatic reselection to DIF_REF1 (indicated by REF_ACK pin).

DIF_REF1

1 1 -0-

LOL to 0: Device locks to DIF_REF1 (assuming valid clock on DIF_REF1).

Re-initialization

-1-

DIF_REF1

1 1 0

REF_SEL set to 1: Prepares for Manual Selection of DIF_REF1 before then re-arming AutoSwitch.

DIF_REF1

1 -0- 0

AUTO set to 0: Manual Select mode entered briefly, manually selecting DIF_REF1 as reference.

DIF_REF1

1 -1- 0

AUTO set to 1: Device is placed in AutoSwitch mode (delay recommended to ensure device fully

locked), re-initializing AutoSwitch with

DIF_REF1 now specified as the initial reference clock.

Table 6: Example AutoSwitch Sequence

P1-P3 P4-P6 P7-P9 P10-P12

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