M2040-01-533.3334T

M2040 Datasheet Rev 1.0 7 of 12 Revised 28Jan2005
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400
M2040
F
REQUENCY
T
RANSLATION
PLL
WITH
A
UTO
S
WITCH
Product Data Sheet
Integrated
Circuit
Systems, Inc.
Hitless Switching Option
Hitless Switching is a device option that can be
specified at time of order. (Please contact ICS.) The
M2040-01 remains in wide bandwidth mode if
NBW = 0.
When
NBW = 0, placing the device into wide bandwidth
operation, the optional Hitless Switching (HS) function
will automatically place the device into narrow
bandwidth operation during reference reselection. This
provides a controlled output clock phase change while
the PLL is acquiring phase lock to a new reference
clock phase. The HS function is trigged by a loss of lock
event. Wide bandwidth is resumed once the PLL
relocks to the input reference. (When the NBW pin = 1,
the device operates in narrow bandwidth continually
and hence the HS mode does not apply).
The HS function is armed after the device locks to the
input clock reference (8 successive phase detector
clock cycles with LOL low). Once armed, HS is
triggered by detection at the phase detector of a single
phase error greater than 4 ns (rising edges).
Once triggered, the HS function narrows the loop band-
width until the PLL is locked to the selected reference (8
successive phase detector clock cycles with LOL low).
When pin AUTO = 1 (automatic reference reselection
mode) HS is used in conjunction with input reselection.
When AUTO = 0 (manual mode), HS will still occur upon
an input phase transient, however the clock input is not
reselected (this enables hitless switching when using an
external MUX for clock selection).
Power-Up Initialization Function (INIT Pin)
The initialization function provides a short-term override
of the narrow bandwidth mode when the device is
powered up in order to facilitate phase locking.
When
INIT is set to logic 1, initialization is enabled. With
NBW set to logic 1 (narrow bandwidth mode), the
initialization function puts the PLL into wide bandwidth
mode until eight consecutive phase detector cycles
occur without a single LOL event. Once the eight valid
PLL locked states have occurred, the PLL bandwidth is
automatically reduced to narrow bandwidth mode.
When
INIT is logic 0, the device is forced into wide
bandwidth mode unconditionally.
External Loop Filter
The M2040 requires the use of an external loop filter
components. These are connected to the provided filter
pins (see Figure 5).
Because of the differential signal path design, the
implementation consists of two identical
complementary RC filters as shown in Figure 5, below.
Figure 5: External Loop Filter
PLL bandwidth is affected by the total “M” (feedback
divider) value, loop filter component values, and other
device parameters. See Table 7, External Loop Filter
Component Values, below.
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
C
POST
C
POST
V
C
nVC
R
POST
nOP_OUTOP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN nOP_IN
6 7549 8
External Loop Filter Component Values
1
VCSO Parameters: K
VCO
= 800kHz/V, VCO Bandwidth = 700kHz. See AC Characteristics on pg. 9 for PLL Loop Constants.
Device Configuration External Loop Filter Component Values
NBW
Mode
2
Nominal Performance Using These Values
F
VCSO
(MHz)
M
Divider
Value
R loop C loop R post C post
PLL Loop
Bandwidth
Damping
Factor
Passband
Peaking (dB)
533.333 30, 32
30k 1.0µF 33k 100pF
1 110 Hz
2.2 0.35
0 3 kHz
10 0.02
Table 7: External Loop Filter Component Values
Note 1: Recommended values for hitless switching. For PLL Simulator software, go to www.icst.com.
Note 2: NBW mode 1 = Narrow Bandwidth, where R
IN
= 2100 k . NBW mode 0 = Wide Bandwidth, where R
IN
= 100 k.
Note 3: This table does not apply to the 400 MHz VCSO option since the Kvco value is different.
M2040 Datasheet Rev 1.0 8 of 12 Revised 28Jan2005
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M2040
F
REQUENCY
T
RANSLATION
PLL
WITH
A
UTO
S
WITCH
Product Data Sheet
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
1
Symbol Parameter Rating Unit
V
I
Inputs -0.5 to V
CC
+0.5 V
V
O
Outputs -0.5 to V
CC
+0.5 V
V
CC
Power Supply Voltage
4.6
V
T
S
Storage Temperature -45 to +100
o
C
Table 8: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability
.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter Min Typ Max Unit
V
CC
Positive Supply Voltage
3.135 3.3 3.465
V
T
A
Ambient Operating Temperature
Commercial
0
+70
o
C
Industrial
-40
+85
o
C
Table 9: Recommended Conditions of Operation
DC Characteristics
Unless stated otherwise, V
CC
=
3.3
V +
5
%,T
A
=
0
o
C
to +
70
o
C (commercial), T
A
=
-40
o
C
to +
85
o
C (industrial), F
VCSO
=
400-534
,
LVPECL outputs terminated with
50
to V
CC
- 2V
Symbol Parameter Min Typ Max Unit Conditions
Power Supply V
CC
Positive Supply Voltage
3.135 3.3 3.465
V
I
CC
Power Supply Current
175 225
mA
Differential
Input: LVDS
/ LVPECL
V
P-P
Peak to Peak Input
Voltage
1
Note 1: Single-ended measurement. See Figure 7, Differential Input Level on pg. 10.
DIF_REF, nDIF_REF
0.15
V
V
CMR
Common Mode Input
1
0.5 V
cc
- 0.85
V
LVCMOS /
LVTTL Input
V
IH
Input High Voltage
REF_SEL, MR_SEL
2
V
cc
+ 0.3 V
V
IL
Input Low Voltage -0.3
1.3
V
Inputs with
Pull-down
I
IH
Input High Current
DIF_REF1, DIF_REF0
150 µA
V
CC
= V
IN
=
3.456V
I
IL
Input Low Current -5 µA
R
pulldown
Internal Pull-down Resistor
51
k
Inputs with
Pull-up
I
IH
Input High Current
FIN_SEL1, FIN_SEL0,
INIT, MR_SEL
5 µA
V
CC
= 3.456V
V
IN
= 0 V
I
IL
Input Low Current -150 µA
R
pullup
Internal Pull-up Resistor
51
k
Inputs biased to Vcc/2
2
Note 2: Biased to Vcc/2, with 50k to Vcc and 50k to ground.
nDIF_REF1, nDIF_REF0 (Note 2)
All Inputs C
IN
Input Capacitance
All Inputs 4
pF
Differential
Outputs
V
OH
Output High Voltage
FOUT1, nFOUT1
FOUT0, nFOUT0
V
cc
- 1.4 V
cc
- 1.0 V
V
OL
Output Low Voltage V
cc
- 2.0 V
cc
- 1.7 V
V
P-P
Peak to Peak Output Voltage
3
Note 3: Single-ended measurement. See Figure 6, Input and Output Rise and Fall Time on pg. 10.
0.4 0.85
V
LVCMO S
Outputs
V
OH
Output High Voltage, Lock
LOL , REF_ACK
2.4 V
CC
V
I
OH
= 1mA
V
OL
Output Low Voltage, Lock
GND 0.4
V
I
OL
= 1mA
Table 10: DC Characteristics
M2040 Datasheet Rev 1.0 9 of 12 Revised 28Jan2005
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400
M2040
F
REQUENCY
T
RANSLATION
PLL
WITH
A
UTO
S
WITCH
Product Data Sheet
Integrated
Circuit
Systems, Inc.
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, V
CC
=
3.3
V +
5
%,T
A
=
0
o
C
to +
70
o
C (commercial), T
A
=
-40
o
C
to +
85
o
C (industrial), F
VCSO
=
400-534
,
LVPECL outputs terminated with
50
to V
CC
- 2V
Symbol Parameter Min Typ Max Unit Conditions
F
IN
Input Frequency
DIF_REF1, nDIF_REF1,
DIF_REF0, nDIF_REF0
200 285
MHz
F
OUT
Output Frequency
FOUT1, nFOUT
1,
FOUT0, nFOUT
0 200 534
MHz
APR VCSO Pull-Range
Commercial
±120 ±200 ppm
Industrial
±50 ±150 ppm
PLL Loop
Constants
1
Note 1: Parameters needed for PLL Simulator software; see Table 7, External Loop Filter Component Values, on pg. 7.
K
VCO
VCO Gain
M2040-xx-400.0000
1600
kHz/V
M2040-xx-533.3334
800
kHz/V
R
IN
Internal Loop Resistor
NBW = 0
100
k
NBW = 1
2100
k
BW
VCSO
VCSO Bandwidth
700
kHz
Phase Noise
and Jitter
Φ n Single Side Band
Phase Noise
@
622.08MHz
1kHz Offset -72 dBc/Hz
10kHz Offset -94 dBc/Hz
100kHz Offset -123 dBc/Hz
J(t) Jitter (rms) 12kHz to 20MHz
0.25 0.5
ps
50kHz to 80MHz
0.25 0.5
ps
odc Output Duty Cycle
2
Note 2: See Parameter Measurement Information on pg. 10.
F
OUT
=200-285MHz P = 2 (P_SEL = 1)
45 50 55
%
F
OUT
= 400-534MHz P = 1 (P_SEL = 0)
40 50 60
%
t
R
Output Rise Time
2
for
FOUT1,
nFOUT1,
FOUT0,
nFOUT0
F
OUT
=200-285MHz P = 2 (P_SEL = 1)
325 425 500
ps
20%
to
80%
F
OUT
= 400-534MHz P = 1 (P_SEL = 0)
200 275 350
ps
t
F
Output Fall Time
2
for
FOUT1,
nFOUT1,
FOUT0,
nFOUT0
F
OUT
=200-285MHz P = 2 (P_SEL = 1)
325 425 500
ps
20%
to
80%
F
OUT
= 400-534MHz P = 1 (P_SEL = 0)
200 275 350
ps
t
LOCK
PLL Lock Time
100
ms
Table 11: AC Characteristics

M2040-01-533.3334T

Mfr. #:
Manufacturer:
Description:
IC PLL FREQ TRANSLATOR 36CLCC
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