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APS12205LLHALX

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
OPERATION
The output of these devices switches low (turns on) when a mag-
netic field perpendicular to the Hall element exceeds the operate
point threshold, B
OP
(see Figure 1). After turn-on, the output volt-
age is V
OUT(SAT)
. The output transistor is capable of continuously
sinking up to 30 mA. When the magnetic field is reduced below
the release point, B
RP
, the device output goes high (turns off).
The difference in the magnetic operate and release points is the
hysteresis, B
HYS ,
of the device. This built-in hysteresis allows
clean switching of the output even in the presence of external
mechanical vibration and electrical noise.
Removal of the magnetic field will leave the device output
latched on if the last crossed switchpoint is B
OP
, or latched off if
the last crossed switch point is B
RP
.
POWER-ON BEHAVIOR
Device power-on occurs once t
ON
has elapsed. During the
time prior to t
ON
, and after V
CC
≥ V
CC
(min), the output state is
V
OUT(SAT)
(Low). After t
ON
has elapsed, the output will corre-
spond with the applied magnetic field for B > B
OP
or B < B
RP
.
See Figure 2 for an example.
Powering-on the device in the hysteresis range (less than B
OP
and
higher than B
RP
) will give an output state of V
OUT(SAT)
. The cor-
rect state is attained after the first excursion beyond B
OP
or B
RP
.
Figure 1: Switching Behavior of Latches
On the horizontal axis, the B+ direction indicates increasing
south polarity magnetic field strength, and the B– direction
indicates decreasing south polarity field strength (including the
case of increasing north polarity.
FUNCTIONAL DESCRIPTION
B
OP
B
RP
B
HYS
V
OUTOFF
V
OUT
V
OUT(SAT)
Switch to Low
Switch to High
B+
B–
V+
0
0
t
t
V
V
CC
(min)
t
ON
0
Output State
Undefined for
V
CC
< V
CC
(min)
POS
V
OUT(SAT )
V
OUTOFF
V
V
OUT
V
CC
POS
B > B
OP
, B
RP
< B < B
OP
B < B
RP
Figure 2: Power-On Timing Diagram
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
11
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
APPLICATIONS
It is strongly recommended that an external bypass capacitor be
connected (in close proximity to the Hall element) between the
supply and ground of the device to guarantee correct performance
under harsh environmental conditions and to reduce noise from
internal circuitry. As is shown in Figure 3, a 0.1 µF capacitor is
typical.
Extensive applications information on magnets and Hall-effect
sensors is available in:
• Hall-Effect IC Applications Guide, AN27701,
• Hall-Effect Devices: Guidelines for Designing Subassemblies
Using Hall-Effect Devices AN27703.1
• Soldering Methods for Allegro’s Products – SMD and
Through-Hole, AN26009
All are provided on the Allegro website:
www.allegromicro.com
C
BYP
APS122xx
VOUT
GND
0.1 µF
VCC
Output
R
L
V
S
Figure 3: Typical Application Circuit
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
12
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Amp
Clock/Logic
Hall Element
Sample and
Hold
Low-Pass
Filter
CHOPPER STABILIZATION
A limiting factor for switchpoint accuracy when using Hall-effect
technology is the small signal voltage developed across the Hall
plate. This voltage is proportionally small relative to the offset
that can be produced at the output of the Hall sensor. This makes
it difficult to process the signal and maintain an accurate, reliable
output over the specified temperature and voltage range. Chopper
stabilization is a proven approach used to minimize Hall offset.
The Allegro technique, dynamic quadrature offset cancellation,
removes key sources of the output drift induced by temperature
and package stress. This offset reduction technique is based on a
signal modulation-demodulation process. Figure 4 illustrates how
it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation. The
subsequent demodulation acts as a modulation process for the
offset, causing the magnetically induced signal to recover its orig-
inal spectrum at baseband while the DC offset becomes a high-
frequency signal. Then, using a low-pass filter, the signal passes
while the modulated DC offset is suppressed. Allegro’s innova-
tive chopper stabilization technique uses a high-frequency clock.
The high-frequency operation allows a greater sampling rate
that produces higher accuracy, reduced jitter, and faster signal
processing. Additionally, filtering is more effective and results in
a lower noise analog signal at the sensor output. Devices such as
the APS12205, APS12215, and APS12235 that use this approach
have an extremely stable quiescent Hall output voltage, are
immune to thermal stress, and have precise recoverability after
temperature cycling. This technique is made possible through the
use of a BiCMOS process which allows the use of low offset and
low noise amplifiers in combination with high-density logic and
sample-and-hold circuits.
Figure 4: Model of Chopper Stabilization
(Dynamic Offset Cancellation)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

APS12205LLHALX

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Hall Effect Sensor 60mA Latch 3.3V/5V Automotive T/R
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