High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
13
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
POWER DERATING
The device must be operated below the maximum junction tem-
perature of the device, T
J
(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating T
J
. (Thermal data is also available on the
Allegro MicroSystems website.)
The Package Thermal Resistance, R
θJA
, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, R
θJC
, is relatively
small component of R
θJA
. Ambient air temperature, T
A
, and air
motion are significant external factors, damped by overmolding.
The resulting power dissipation capability directly reflects upon
the ability of the device to withstand extreme operating condi-
tions. The junction temperature mission profile specified in the
Absolute Maximum Ratings table designates a total operating life
capability based on qualification for the most extreme conditions,
where T
J
may reach 175°C.
The silicon IC is heated internally when current is flowing into
the VCC terminal. When the output is on, current sinking into the
VOUT terminal generates additional heat. This may increase the
junction temperature, T
J
, above the surrounding ambient tempe-
rature. The APS12205, APS12215, and APS12235 are permitted
to operate up to T
J
= 175°C. As mentioned above, an operating
device will increase T
J
according to equations 1, 2, and 3 below.
This allows an estimation of the maximum ambient operating
temperature.
P
D
= V
IN
×
I
IN
(1)
ΔT = P
D
×
R
θJA
(2)
T
J
= T
A
+ ΔT (3)
For example, given common conditions such as: T
A
= 25°C,
V
CC
= 5 V, I
CC
= 2.5 mA, V
OUT
= 185 mV, I
OUT
= 2 mA (output
on), and R
θJA
= 165°C/W, then:
P
D
= (V
CC
× I
CC
) + (V
OUT
× I
OUT
) =
(5 V × 2.5 mA) + (185 mV × 2 mA) =
12.5 mW + 0.4 mW = 12.9 mW
ΔT = P
D
× R
θJA
= 12.9 mW × 165°C/W = 2.1°C
T
J
= T
A
+ ΔT = 25°C + 2.1°C = 27.1°C
A worst-case estimate, P
D
(max), represents the maximum allow-
able power level (V
CC
(max), I
CC
(max)), without exceeding
T
J
(max), at a selected R
θJA
.
For example, given the conditions R
θJA
= 228°C/W, T
J
(max) =
175°C, V
CC
(max) = 5.5 V, I
CC
(max) = 4 mA, V
OUT
= 500 mV,
and I
OUT
= 5 mA (output on), the maximum allowable operating
ambient temperature can be determined.
The power dissipation required for the output is shown below:
P
D
(V
OUT
) = V
OUT
× I
OUT
= 500 mV × 5 mA = 2.5 mW
The power dissipation required for the IC supply is shown below:
P
D
(V
CC
) = V
CC
× I
CC
= 5.5 V × 4 mA = 22 mW
Next, by inverting using equation 2:
ΔT = P
D
× R
θJA
= [P
D
(V
OUT
) + P
D
(V
CC
)] × 228°C/W =
(2.5 mW + 22 mW) × 228°C/W =
24.5 mW × 228°C/W = 5.6°C
Finally, by inverting equation 3 with respect to voltage:
T
A
(est) = T
J
(max) – ΔT = 175°C – 5.6°C = 169.4°C
In the above case there is only sufficient power dissipation capa-
bility to operate up to T
A
(est). This particular result indicates that,
at T
J
(max), the application and device can only dissipate adequate
amounts of heat at ambient temperatures ≤ T
A
(est).
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
14
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
0.55 REF
Gauge Plane
Seating Plane
0.25 BSC
0.95 BSC
0.95
1.00
0.70
2.40
2
1
A
Active Area Depth, 0.28 mm REF
B
C
B
Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Branding scale and appearance at supplier discretion
A
PCB Layout Reference View
Branded Face
C
Standard Branding Reference View
APS12205LLHA
1
A04
APS12215LLHA
1
A01
APS12235LLHA
1
A35
2.90
+0.10
–0.20
4°±4°
8X 10° REF
0.180
+0.020
–0.053
0.05
+0.10
–0.05
0.25 MIN
1.91
+0.19
–0.06
2.98
+0.12
–0.08
1.00 ±0.13
0.40 ±0.10
For Reference Only; not for tooling use (reference dwg. 802840)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
D
Hall element, not to scale
D
D
D
1.49
0.96
3
Package LH, 3-Pin (SOT-23W)
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APS12205,
APS12215,
and APS12235
15
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package UA, 3-Pin SIP
2 31
1.27 NOM
1.02
MAX
45°
45°
C
1.52 ±0.05
B
A
E
E
1.44
2.04
E
Gate and tie bar burr area
A
B
C
Dambar removal protrusion (6X)
D
E
Active Area Depth, 0.50 mm REF
Branding scale and appearance at supplier discretion
Hall element (not to scale)
For Reference Only; not for tooling use (reference DWG-9065)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Mold Ejector
Pin Indent
D
Standard Branding Reference View
A18
1
APS12205LUAA
A03
1
APS12215LUAA
A36
1
APS12235LUAA
0.41
+0.03
–0.06
0.43
+0.05
–0.07
14.99 ±0.25
4.09
+0.08
–0.05
3.02
+0.08
–0.05
0.79 REF
10°
Branded
Face

APS12205LLHALX

Mfr. #:
Manufacturer:
Description:
Hall Effect Sensor 60mA Latch 3.3V/5V Automotive T/R
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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