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858S011AKILFT

P1-P3P4-P6P7-P9P10-P12P13-P14
10© Integrated Device Technology, Inc. September 19, 2017
ICS858S011I Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDERSOLDER
PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA
11© Integrated Device Technology, Inc. September 19, 2017
ICS858S011I Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS858S011I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS858S011I is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
• Power (core)
MAX
= V
DD_MAX
* I
DD
= 3.63V * 57mA = 206.9mW
• Power Dissipation for internal termination R
T
Power (R
T
)
MAX
= 4 * (V
IN_MAX
)
2
/ R
T_MIN
= (1.2V)
2
/ 80 = 72mW
Total Power_
MAX
= 206.9mW + 72mW = 278.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 74.7°C/W per Table 4 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.279W * 74.7°C/W = 105.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 4. Thermal Resistance
JA
for 16 Lead VFQFN, Forced Convection
Reliability Information
Table 5.
JA
vs. Air Flow Table for a 16 Lead VFQFN
Transistor Count
The transistor count for ICS858S011I is: 216
Pin Compatible with 858011
JA
by Velocity
Meters per Second 0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 74.7°C/W 65.3°C/W 58.5°C/W
JA
vs. Air Flow
Meters per Second 0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 74.7°C/W 65.3°C/W 58.5°C/W
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual
property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
Tech Support
www.IDT.com/go/support
Sales
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
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www.IDT.com
12© Integrated Device Technology, Inc. September 19, 2017
ICS858S011I Datasheet
Package Outline Drawings
The package outline drawings are located in the last section of this document. The package information is the most current data available and
is subject to change without notice or revision of this document.
Ordering Information
Table 7. Ordering Information
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Revision History
Part/Order Number Marking Package Shipping Packaging Temperature
858S011AKILF 011A “Lead-Free” 16 Lead VFQFN Tube -40C to 85C
858S011AKILFT 011A “Lead-Free” 16 Lead VFQFN 2500 Tape & Reel -40C to 85C
Revision Date Description of Change
September 19, 2017
Updated the package outline drawings; however, no mechanical changes
Completed other minor improvements
October 12, 2010 Initial release.
P1-P3P4-P6P7-P9P10-P12P13-P14

858S011AKILFT

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Description:
Clock Drivers & Distribution Low Skew,1-to-2,Diff CML Fanout Buffer
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