4© Integrated Device Technology, Inc. September 19, 2017
ICS858S011I Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator “Rohde & Schwarz SMA100A Low Noise
Signal Generator as external input to an Agilent 8133A 3GHz Pulse
Generator”.
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.042ps (typical)
5© Integrated Device Technology, Inc. September 19, 2017
ICS858S011I Datasheet
Parameter Measurement Information
CML Output Load AC Test Circuit
Part-to-Part Skew
Single-ended & Differential Input Voltage Swing
Differential Input Level
Output Skew
Propagation Delay
SCOPE
Qx
Power
Supply
V
EE
V
CC
CML Driver
0V
-2.375V to -3.63V
tsk(pp)
P
art 1
P
art 2
Qx
nQx
Qy
nQy
V
IN
, V
OUT
400mV
(typical)
V
DIFF_IN
, V
DIFF_OU
T
800mV
(typical)
V
IH
Cross Points
V
IN
V
IL
IN
nIN
V
CC
V
EE
Qx
nQx
Qy
nQy
t
PD
nQ0, nQ1
Q0, Q1
IN
nIN
6© Integrated Device Technology, Inc. September 19, 2017
ICS858S011I Datasheet
Parameter Measurement Information, continued
Output Rise/Fall Time
Applications Information
Recommendations for Unused Output Pins
Outputs:
CML Outputs
All unused CML outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
nQ0, nQ1
Q0, Q1

858S011AKILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution Low Skew,1-to-2,Diff CML Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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