72V73260BBG8 Datasheet 72V73260BBG8, 72V73260BBG | P4-P6

INDUSTRIAL TEMPERATURE RANGE

IDT72V73260 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 16,384 x 16,384

PIN DESCRIPTION

SYMBOL NAME I/O DESCRIPTION

A0-15 Address 0 to 15 I These address lines access all internal memories.

C32i Clock I Serial clock for shifting data in/out on the serial data stream. This input accepts a 32.768 MHz clock.

CS Chip Select I This active LOW input is used by a microprocessor to activate the microprocessor port of IDT72V73260.

D0-15 Data Bus 0-15 I/O These pins are the data bits of the microprocessor port.

DS Data Strobe I This active LOW input works in conjunction with CS to enable the read and write operations and sets the

data bus lines (D0-D15).

DTA Data Transfer O Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then goes

Acknowledgment high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required

to hold a HIGH level when the pin is in high-impedance.

FE Frame Evaluation I This input can be used to measure delay in the data path by comparing the frame pulse, F32i, with this input.

F32i Frame Pulse I This input accepts and automatically identifies frame synchronization signals formatted according to

ST-BUS

and GCI specifications.

GND Ground Ground Rail

ODE Output Drive Enable I This is the output enable control for the TX serial outputs. When the ODE input is LOW and the Output Stand

By bit of the Control Register is LOW, all TX outputs are in a high-impedance state. If this input is HIGH, the TX

output drivers are enabled. However, each channel may still be put into a high-impedance state by using the

per-channel control bits in the Connection Memory.

RESET Device Reset I This input puts the IDT72V73260 into a reset state that clears the device internal counters, registers and

brings TX0-31 and D0-D15 into a high-impedance state. The RESET pin must be held LOW for a minimum

of 20ns to properly reset the device.

R/W Read/Write I This input controls the direction of the data bus lines (D0-D15) during a microprocessor access.

RX0-31 Data Stream I Serial data input stream. These streams have a data rate of 32.768Mb/s.

Input 0 to 31

TCK Test Clock I Provides the clock to the JTAG test logic.

TDI Test Serial Data In I JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up

when not driven.

TDO Test Serial Data Out O JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state

when JTAG scan is not enabled.

TMS Test Mode Select I JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal

pull-up when not driven.

TRST Test Reset I Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is

pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW,

to ensure that the IDT72V73260 is in the normal functional mode.

TX0-15 TX Output 0 to 15 O Serial data output stream. These streams have a data rate of 32.768Mb/s.

(Three-State Outputs)

TX16-31/ TX Output 16 to 31/ O When all 32 output streams are selected via Control Register, these pins are the output streams TX16 to TX31

OEI0-15 Output Enable and operate at 32.768Mb/s. When output enable function is selected, these pins reflect the active or

Indication 0 to 15 high-impedance status for the corresponding output stream Output Enable Indication0-15.

(Three-State Outputs)

VCC VCC +3.3 Volt Power Supply.

INDUSTRIAL TEMPERATURE RANGE

IDT72V73260 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 16,384 x 16,384

DESCRIPTION (CONTINUED)

The IDT72V73260 is capable of switching up to 16,384 x 16,384 channels

without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the

device maintains frame integrity in data applications and minimizes throughput

delay for voice applications on a per-channel basis.

The 32 serial input streams (RX) of the IDT72V73260 are run at 32.768Mb/s

allowing 512 channels per 125μs frame. The data rates on the output streams

(TX) are identical to those on the input streams (RX).

With two main operating modes, Processor Mode and Connection Mode, the

IDT72V73260 can easily switch data from incoming serial streams (Data

Memory) or from the controlling microprocessor via Connection Memory. As

control and status information is critical in data transmission, the Processor Mode

is especially useful when there are multiple devices sharing the input and output

streams.

With data coming from multiple sources and through different paths, data

entering the device is often delayed. To handle this problem, the IDT72V73260

has a Frame Evaluation feature to allow individual streams to be offset from the

frame pulse in half clock-cycle intervals up to +7.5 clock cycles.

The IDT72V73260 also provides a JTAG test access port, memory block

programming, a simple microprocessor interface and automatic ST-BUS

/GCI

sensing to shorten setup time, aid in debugging and ease use of the device

without sacrificing capabilities.

FUNCTIONAL DESCRIPTION

DATA AND CONNECTION MEMORY

All data that comes in through the RX inputs go through a serial-to-parallel

conversion before being stored into internal Data Memory. The 8 KHz frame

pulse (F32i) is used to mark the 125μs frame boundaries and to sequentially

address the input channels in Data Memory.

Data output on the TX streams may come from either the serial input streams

(Data Memory) or from the microprocessor (Connection Memory). In the case

that RX input data is to be output, the addresses in Connection Memory are used

to specify a stream and channel of the input. The Connection Memory is setup

in such a way that each location corresponds to an output channel for each

particular stream. In that way, more than one channel can output the same data.

In Processor Mode, the microprocessor writes data to the Connection Memory

locations corresponding to the stream and channel that is to be output. The lower

half (8 least significant bits) of the Connection Memory is output every frame until

the microprocessor changes the data or mode of the channel. By using this

Processor Mode capability, the microprocessor can access input and output

time-slots on a per-channel basis.

The two most significant bits of the Connection Memory are used to control

per-channel mode of the out put streams. Specifically, the MOD1-0 bits are used

to select Processor Mode, Constant or Variable delay Mode, and the high-

impedance state of output drivers. If the MOD1-0 bits are set to 1-1 accordingly,

only that particular output channel (8 bits) will be in the high-impedance state.

If however, the ODE input pin is LOW and the Output Standby Bit in the Control

particular channel in Connection Memory has enabled the output for that

channel. In other words, the ODE pin and Output Stand By control bit are master

output enables for the device (See Table 3).

SERIAL DATA INTERFACE TIMING

For a 32.768Mb/s serial data rate , the master clock frequency will be running

at 32.768 MHz resulting in a single-bit per clock. The IDT72V73260 provides

two different interface timing modes, ST-BUS

or GCI.

The IDT72V73260 automatically detects the presence of an input frame

pulse and identifies it as either ST-BUS

or GCI. In ST-BUS

Mode, data is

clocked out on the falling edge and is clocked in on the subsequent rising-edge.

See Figure 14 for timing. In GCI Mode, data is clocked out on the rising edge

and is clocked in on the subsequent falling edge. See Figure 15 for timing.

INPUT FRAME OFFSET SELECTION

Input frame offset selection allows the channel alignment of individual input

streams to be offset with respect to the output stream channel alignment. Although

all input data comes in at the same speed, delays can be caused by variable

path serial backplanes and variable path lengths which may be implemented

in large centralized and distributed switching systems. Because data is often

delayed, this feature is useful in compensating for the skew between input

streams.

Each input stream can have its own delay offset value by programming the

frame input offset registers (FOR, Table 8). The maximum allowable skew is +7.5

master clock (C32i) periods forward with a resolution of ½ clock period, see

Table 9. The output frame cannot be adjusted.

SERIAL INPUT FRAME ALIGNMENT EVALUATION

The IDT72V73260 provides the Frame Evaluation input to determine

different data input delays with respect to the frame pulse F32i. A measurement

cycle is started by setting the Start Frame Evaluation bit of the Control Register

LOW for at least one frame. When the Start Frame Evaluation bit in the Control

the Complete Frame Evaluation bit of the Frame Alignment Register changes

from LOW to HIGH to signal that a valid offset measurement is ready to be read

from bits 0 to 12 of the Frame Alignment Register . The Start Frame Evaluation

bit must be set to zero before a new measurement cycle is started.

In ST-BUS

mode, the falling edge of the frame measurement signal (Frame

Evaluation) is evaluated against the falling edge of the ST-BUS

frame pulse.

In GCI mode, the rising edge of Frame Evaluation is evaluated against the rising

edge of the GCI frame pulse. See Table 7 and Figure 1 for the description of

the Frame Alignment Register.

MEMORY BLOCK PROGRAMMING

The IDT72V73260 provides users with the capability of initializing the entire

Connection Memory block in two frames. To set bits 14 and 15 of every

Connection Memory location, first program the desired pattern in the Block

Programming Data Bits (BPD 1-0), located in bits 7 and 8 of the Control Register.

The block programming mode is enabled by setting the Memory Block

Program bit of the Control Register HIGH. When the Block Programming Enable

bit of the Control Register is set to HIGH, the Block Programming data will be

loaded into the bits 14 and 15 of every Connection Memory location. The other

Connection Memory bits (bit 0 to bit 13) are loaded with zeros. When the memory

block programming is complete, the device resets the Block Programming

Enable, BPD 1-0 and Memory Block Program bits to zero.

INDUSTRIAL TEMPERATURE RANGE

IDT72V73260 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 16,384 x 16,384

DELAY THROUGH THE IDT72V73260

The switching of information from the input serial streams to the output serial

streams results in a throughput delay. The device can be programmed to

perform time-slot interchange functions with different throughput delay capabili-

ties on a per-channel basis. For voice applications, variable throughput delay

is best as it ensure minimum delay between input and output data. In wideband

data applications, constant throughput delay is best as the frame integrity of the

information is maintained through the switch.

The delay through the device varies according to the type of throughput delay

selected in the MOD bits of the Connection Memory.

VARIABLE DELAY MODE (MOD1-0 = 0-0)

In this mode, the delay is dependent only on the combination of source and

destination channels and is independent of input and output streams. The

minimum delay achievable in the IDT72V73260 is three time-slots. If the input

channel data is switched to the same output channel (channel n, frame p), it will

be output in the following frame (channel n, frame p+1). The same is true if the

input channel n is switched to output channel n+1 or n+2. If the input channel

n is switched to output channel n+3, n+4,..., the new output data will appear in

the same frame. Table 2 shows the possible delays for the IDT72V73260 in

Variable Delay mode.

CONSTANT DELAY MODE (MOD1-0 = 0-1)

In this mode, frame integrity is maintained in all switching configurations by

making use of a multiple data memory buffer. Input channel data is written into

the data memory buffers during frame n will be read out during frame n+2. In

the IDT72V73260, the minimum throughput delay achievable in Constant Delay

mode will be one frame plus one channel. See Table 1.

MICROPROCESSOR INTERFACE

The IDT72V73260’s microprocessor interface looks like a standard RAM

interface to improve integration into a system. With a 16-bit address bus and a

16-bit data bus, reads and writes are mapped directly into Data and Connection

memories. By allowing the internal memories to be randomly accessed, the

controlling microprocessor has more time to manage other peripheral devices

and can more easily and quickly gather information and setup the switch paths.

Table 4 shows the mapping of the addresses into internal memory blocks.

MEMORY MAPPING

The address bus on the microprocessor interface selects the internal registers

and memories of the IDT72V73260.

The two most significant bits of the address select between the registers, Data

Memory, and Connection Memory. If A15 and A14 are HIGH, A13-A0 are used

to address the Data Memory. If A15 is HIGH and A14 is LOW, A13-A0 are used

to address Connection Memory. If A15 is LOW and A14 is HIGH A13-A0 are

used to select the Control Register, Frame Alignment Register, and Frame Offset

Registers. See Table 4 for mappings.

As explained in the Initialization sections, after system power-up, the Control

configuration.

The data in the Control Register consists of the Memory Block Programming

bit , the Block Programming Data bits, the Begin Block Programming Enable,

the Output Stand By, Start Frame Evaluation, Output Enable Indication and

Software Reset . As explained in the Memory Block Programming section, the

Block Programming Enable begins the programming if the Memory Block

Program bit is enabled. This allows the entire Connection Memory block to be

programmed with the Block Programming Data bits. If the ODE pin is LOW, the

Output Stand By bit enables (if HIGH) or disables (if LOW) all TX output drivers.

If the ODE pin is HIGH, the contents of the Output Stand By bit is ignored and

all TX output drivers are enabled.

SOFTWARE RESET

The Software Reset serves the same function as the hardware reset. As

with the hard reset, the Software Reset must also be set HIGH for 20ns before

bringing the Software Reset LOW again for normal operation. Once the Software

Reset is LOW, internal registers and other memories may be read or written.

During Software Reset, the microprocessor port is still able to read from all

internal memories. The only write operation allowed during a Software Reset

is to the Software Reset bit in the Control Register to complete the Software Reset.

CONNECTION MEMORY CONTROL

If the ODE pin and the Output Stand By bit are LOW, all output channels will

be in three-state. See Table 3 for detail.

If MOD1-0 of the Connection Memory is 1-0 accordingly, the output channel

will be in Processor Mode. In this case the lower eight bits of the Connection

Memory are output each frame until the MOD1-0 bits are changed. If MOD1-

0 of the Connection Memory are 0-1 accordingly, the channel will be in Constant

Delay Mode and bits 13-0 are used to address a location in Data Memory. If

MOD1-0 of the Connection Memory are 0-0, the channel will be in Variable

Delay Mode and bits 13-0 are used to address a location in Data Memory. If

MOD 1-0 of the Connection Memory are 1-1, the channel will be in high-

Impedance mode and that channel will be in three-state.

OUTPUT ENABLE INDICATION

The IDT72V73260 has the capability to indicate the state of the outputs (active

or three-state) by enabling the Output Enable Indication in the Control Register.

In the Output Enable Indication mode however, only half of the output streams

are available. If this same capability is desired with all 32 streams, this can be

accomplished by using two IDT72V73260 devices. In one device, the All Output

Enable bit is set to a one while in the other the All Output Enable is set to zero.

In this way, one device acts as the switch and the other as a three-state control

device, see Figure 5. It is important to note if the TSI device is programmed for

All Output Enable and the Output Enable Indication is also set, the device will

be in the All Output Enable mode not Output Enable Indication. To use all 32

streams, set Output Enable Indication in the Control Register to zero.

INITIALIZATION OF THE IDT72V73260

After power up, the state of the Connection Memory is unknown. As such,

the outputs should be put in high-impedance by holding the ODE pin LOW. While

the ODE is LOW, the microprocessor can initialize the device by using the Block

Programming feature and program the active paths via the microprocessor bus.

Once the device is configured, the ODE pin (or Output Stand By bit depending

on initialization) can be switched to enable the TSI switch.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

72V73260BBG8

Mfr. #:

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Description:

Digital Bus Switch ICs 16K x 16K TSI 32 I/O 32Mbps, 3.3V

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72V73260BBG8

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