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R2A20168NP#W5

P1-P3P4-P6P7-P9P10-P10
Datasheet
R03DS0019EJ0200
Rev.2.00
Jul 03, 2013
Page 1 of 9
R03DS0019EJ0200 Rev.2.00
Jul 03, 2013
8-bit 8ch D/A Converter with Buffer Amplifiers
R2A20168NP/SA/SP
Block Diagram
Features
Description
· Guarantee Nonlinearity error : +/-1.0LSB, Differential nonlinearity error : +/-0.7LSB
· Data transfer format: 12-bit serial data input type by 3 wire ( DI, SCK, LD )
· Output buffer op-amps: Operable over entire voltage range from almost ground to Vcc ( 0 to 5V )
· Very small size package line-up: QFN-16(pin pitch: 0.5mm), TSSOP-16(pin pitch 0.65mm)
The R2A20168 is an integrated circuit semiconductor of CMOS structure with 8 channels of built in D/A
unnecessary and enabling configuration of a system with few component parts.
Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD.
Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink source, and
can operate over the entire voltage range from almost ground to Vcc ( 0 to 5V ), making peripheral elements
unnecessary and enabling configuration of a system with few component parts.
Very small QFN package is added to lineup. It is suitable for a small mounting and reduces the mounting area.
· Conversion from digital data to analog control data for home-use and industrial equipment.
· Signal gain control or automatic adjustment of LCD-TV, PDP-TV or LCD display-monitor.
· Blurring correction control or various control of the interchangeable lens of digital still camera.
· Automatic adjustment by combination with microcomputer and EEPROM.
(substitution of half fixed resistance)
Application
Number for SOP/TSSOP package
Number for QFN package
16
9
12
8
Channel decoder
15
GND
LD
Vcc
Ao1
1
V
refL
8
V
refU
10
Ao8
8-bit upper
segment R-2R
1 3 2 4 6 5 7 8
2
Ao2
3
Ao3
4
Ao4
5
Ao5
6
Ao6
7
Ao7
10
13
16
1
2
3
4
5
8
6 15
7
14
12-bit shift register
13
14
CLK
DI
11
DO
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
11
9
12
1 8
Power on
reset
8-bit upper
segment R-2R
8
8-bit latch
8–bit latch
Datasheet
R2A20168NP/SA/SP
Page 2 of 9
R03DS0019EJ0200 Rev.2.00
Jul 03, 2013
Pin Description
Pin Arrangement
Pin No.
Symbol Function
[QFN]
[TSSO
P
/SOP]
12 14 DI
Serial data input terminal.
( Input serial data with a 12-bit data length )
11 13 CLK
Serial clock input terminal
(Input signal from DI terminal is input to 12-bit shift register at rise of
serial clock.)
10 12 LD
Load terminal
(When High level is input to LD terminal, value in 12-bit shift register
is loaded into decoder and 8-bit latch.)
9 11 Do
Serial data output terminal
(Data is sequentially output from the MSB bit.)
13 15 Ao1
8-bit resolution D/A converter output terminals
(After power on, all channels are reset and DAC data 00h is output.)
16 2 Ao2
1 3 Ao3
2 4 Ao4
3 5 Ao5
4 6 Ao6
5 7 Ao7
8 10 Ao8
7 9 Vcc Power supply terminal
14 16 GND
GND terminal
6 8
V
refU
D/A converter upper reference voltage input terminal
15 1
V
refL
D/A converter lower reference voltage input terminal
R2A20168SA/SP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R2A20168NP (Top view)
R2A20168SA/SP (Top view)
12
11
10
9
1
2
3
4
Outline: PWQN0016KB-A [NP]
5
6
7
8
16
15
14
13
R2A20168NP
Outline: PTSP0016JB-A [SA]
PRSP0016DH-B [SP]
Ao2
Ao3
Ao4
LD
DO
Ao8
Vcc
Ao5
Ao6
Ao7
CLK
DI
Ao1
GND
V
refL
V
refU
Ao2
Ao3
GND
Ao1
DI
CLK
Ao4
Ao5
Ao6
Ao7
LD
DO
Ao8
Vcc
V
refL
V
refU
Datasheet
R2A20168NP/SA/SP
Page 3 of 9
R03DS0019EJ0200 Rev.2.00
Jul 03, 2013
Absolute Maximum Ratings
Item Symbol Conditions Ratings Unit
Supply voltage Vcc -0.3 to +6.5 V
D/A converter upper reference voltage V
refU -0.3 to +6.5 V
D/A converter lower reference voltage
VrefL -0.3 to +6.5 V
Buffer amplifier output current
I
AO
Continuous
-2.0 to +2.0 mA
Input voltage Vin
-0.3 to Vcc+0.3 <+6.5 V
Output voltage Vo
-0.3 to Vcc+0.3 <+6.5 V
Power dissipation Pd Ta= +85deg
290(NP) / 150(SA) / 300(SP)
mW
Thermal derating factor K theta Ta> +25deg 7.25(NP) / 3.75(SA) / 7.5(SP) mW/deg
Operating temperature Topr -30 to +85 deg
Storage temperature Tstg -40 to +125 deg
Electrical Characteristics
*1 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered
on quickly, initialize is not operate. So, keep the time period of re-powered on (t
POR
).
Vcc
Internal
Reset signal
tPOR
trVcc
< 0.1V
(equivalent to trVcc)
VccPOR
Resetting period
GND
GND
Resetting period
« Digital Part » ( Vcc, VrefU = +5V +/-10%, Vcc>VrefU, GND,VrefL =0V, Ta= -30 to +85deg, Unless otherwise noted )
(Ta= +25deg unless otherwise noted)
Item Symbol Test conditions
Limits
Unit
Min Typ Max
Supply voltage Vcc 2.7 5.0 5.5 V
Supply current Icc CLK =1MHz, Vcc =5V, I
AO =0µA - 0.4 1.2 mA
Input leak current I
ILK VIN = 0 to Vcc -10 - 10 µA
Input low voltage V
IL - - 0.2Vcc V
Input high voltage V
IH
4.0V < Vcc
0.55Vcc - - V
Vcc £ 4.0V
0.8Vcc - - V
Output low voltage V
OL
4.0V < Vcc, IOL = 2.0mA - - 0.4 V
Vcc < 4.0V, I
OL = 1.5mA - - 0.4 V
Output high voltage V
OH IOH = -400µA
Vcc –
0.4
- - V
Supply voltage
rise time *1
trVcc
Vcc = 0 to 2.7V 100 - - µs
Internal reset
operating voltage *1
Vcc
POR Vcc = 0 to 2.7V - 1.5 1.9 V
Power supply restart
interval (Power supply
OFF à ON) *1
tPOR
Vcc < 0.1V 1 - - ms
P1-P3P4-P6P7-P9P10-P10

R2A20168NP#W5

Mfr. #:
Buy R2A20168NP#W5
Manufacturer:
Renesas Electronics
Description:
Digital to Analog Converters - DAC I2C Bus I/O Expander
Lifecycle:
New from this manufacturer.
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