MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER
MP1907 Rev. 1.2 www.MonolithicPower.com 12
4/16/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
OPERATION
Switch Shoot-through Protection
The input signals of INH and INL are controlled
independently. Input shoot-through protection
circuitry is implemented to prevent shoot-
through between the HSFET and LSFET
outputs. Only one of the FET drivers can be ON
at one time. If both INH and INL are high at the
same time, both HSFET and LSFET will be
OFF.
Under Voltage Lock Out
When VDD or BST goes below their respective
UVLO thresholds, both DRVH and DRVL
outputs will go low to turn off both FETs. Once
VDD rises above the UVLO threshold, both
DRVH and DRVL will stay low until a rising
edge is detected on either INH or INL.
The truth table in Table 1 details the operation
of the HSFET and LSFET under different INH,
INL and UVLO conditions
Table1 States of Driver Output under different conditions
EN
BST-SW
Voltage
V
DD
Voltage INH INL DRVH DRVL
UVLO Latch
status
Operating
Condition
0 X X X X Open
200kΩ
pull down
X X
X X 0 0 0 0 X
X X 1 1 0 0 X
X Above UVLO 0 1 0 1 Normal
Above
UVLO
Above UVLO 1 0 1 0 Normal
Normal Operation
Falls below
UVLO
Above UVLO X X 0 0
Normal to
Tripped
Above
UVLO
Falls below
UVLO
X X 0 0
Normal to
Tripped
Normal-to-Tripped
Transition
X Above UVLO 0 or 1 0 or 1 0 0 Tripped
X Below UVLO X X 0 0 Tripped
When UVLO latch is
tripped.
X Above UVLO 0 to 1 0 to 1 0 0
Tripped, Reset
by INL & INH
X Above UVLO 1 to 0 1 0 0 to 1
Tripped, Reset
by INH Falling
Below
UVLO
Above UVLO 1 1 to 0 0 0
Tripped, Reset
by INL Falling
Above
UVLO
Above UVLO 1 1 to 0 0 to 1 0
Tripped, Reset
by INL Falling
Below
UVLO
Above UVLO 0 0 to 1 0 0 to 1
Tripped, Reset
by INL
Below
UVLO
Above UVLO 0 to 1 0 0 0
Tripped, Reset
by INH
1
Above
UVLO
Above UVLO 0 to 1 0 0 to 1 0
Tripped, Reset
by INH
Tripped to Normal
Transition
Note: x = Don’t Care.
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