CPC7583BATR Datasheet CPC7583BATR, CPC7583BA | P16-P18

NTEGRATED

IRCUITS

IVISION

16 www.ixysic.com R07

CPC7583

2.4 Data Latch

The CPC7583 has an integrated data latch. The latch

operation is controlled by logic-level input at the

LATCH pin. The data input of the latch are the input

pins, while the output of the data latch is an internal

node used for state control. When the LATCH control

pin is at logic 0, the data latch is transparent and data

control signals flow directly through to state control. A

change in input will be reflected by a change in switch

state. When the LATCH control pin is at logic 1, the

data latch is active and a change in input control will

not affect switch state. The switches will remain in the

position they were in when the LATCH changed from

logic 0 to logic 1 and will not respond to changes in

input as long as the latch is at logic 1. The T

input is

not tied to the data latch. Therefore, T

is not

affected by the LATCH input and the T

input will

override state control.

2.5 T

Behavior

Setting T

to +5V allows switch control using the

logic inputs. This setting, however, also disables the

thermal shutdown circuit and is therefore not

recommended. When using logic control via the input

pins, T

should be allowed to float. As a result, the

two recommended states when using T

as a control

are 0, which forces the device to an all-off state, or

float, which allows logic inputs to remain active. This

requires the use of an open-collector type buffer.

2.6 Ringing Switch Zero-Cross Current Turn Off

After the application of a logic input to turn SW4 off,

the ringing switch is designed to delay the change in

state until the next zero-crossing. Once on, the switch

requires a zero-current cross to turn off, and therefore

should not be used to switch a pure DC signal. The

switch will remain in the on state no matter the logic

input until the next zero crossing. These switching

characteristics will reduce and possibly eliminate

overall system impulse noise normally associated with

ringing switches. See IXYS Integrated Circuits

Division’s application note AN-144, Impulse Noise

Benefits of Line Card Access Switches for more

information. The attributes of ringing switch SW4 may

make it possible to eliminate the need for a zero-cross

switching scheme. A minimum impedance of 300 in

series with the ringing generator is recommended.

2.7 Power Supplies

Both a +5 V supply and battery voltage are connected

to the CPC7583. Switch state control is powered

exclusively by the +5 V supply. As a result, the

CPC7583 exhibits extremely low power consumption

during both active and idle states.

The battery voltage is not used for switch control but

rather as a supply for the integrated secondary

protection circuitry. The integrated SCR is designed to

trigger when the voltage at T

BAT

or R

BAT

drops 2 to

4 V below the applied voltage on the V

BAT

pin. This

trigger prevents a fault induced overvoltage event at

the T

BAT

or R

BAT

nodes.

2.8 Battery Voltage Monitor

The CPC7583 also uses the V

BAT

voltage to monitor

battery voltage. If battery voltage is lost, the CPC7583

immediately enters the all-off state. It remains in this

state until the battery voltage is restored. The device

also enters the all-off state if the system battery

voltage goes more positive than –10 V, and remains in

the all-off state until the battery voltage goes more

negative than –15 V. This battery monitor feature

draws a small current from the battery (less than 1 A

typical) and will add slightly to the device’s overall

power dissipation.

2.9 Protection

2.9.1 Diode Bridge/SCR

The CPC7583 uses a combination of current limited

break switches, a diode bridge/SCR clamping circuit,

and a thermal shutdown mechanism to protect the

SLIC device or other associated circuitry from damage

during line transient events such as lightning. During a

positive transient condition, the fault current is

conducted through the diode bridge to ground via

GND

. Voltage is clamped to a diode drop above

ground. During a negative transient of 2V to 4V more

negative than the voltage source at V

BAT

, the SCR

conducts and faults are shunted to F

GND

via the SCR

or the diode bridge.

In order for the SCR to crowbar or foldback, the on

voltage (see “Protection Circuitry Electrical

Specifications” on page 12) of the SCR must be less

negative than the V

BAT

voltage. If the V

BAT

voltage is

less negative than the SCR on voltage, or if the V

BAT

supply is unable to source the trigger current, the SCR

will not crowbar.

NTEGRATED

IRCUITS

IVISION

CPC7583

R07 www.ixysic.com 17

For power induction or power-cross fault conditions,

the positive cycle of the transient is clamped to a diode

drop above ground and the fault current directed to

ground. The negative cycle of the transient will cause

the SCR to conduct when the voltage exceeds the

BAT

reference voltage by two to four volts, steering

the fault current to ground.

2.9.2 Current Limiting function

If a lightning strike transient occurs when the device is

in the talk state, the current is passed along the line to

the integrated protection circuitry and restricted by the

dynamic current limit response of the active switches.

During the talk state when a 1000V 10x1000 S pulse

(GR-1089-CORE lightning) is applied to the line

though a properly clamped external protector, the

current into T

LINE

or R

LINE

will be a pulse with a typical

magnitude of 2.5 A and a duration of less than 0.5 s.

If a power-cross fault occurs with the device in the talk

state, the current is passed though break switches

SW1 and SW2 on to the integrated protection circuit

and is limited by the dynamic DC current limit

response of the two break switches. The DC current

limit, specified over temperature, is between 80 mA

and 425 mA, and the circuitry has a negative

temperature coefficient. As a result, if the device is

subjected to extended heating due to power cross

fault, the measured current at T

LINE

or R

LINE

will

decrease as the device temperature increases. If the

device temperature rises sufficiently, the temperature

shutdown mechanism will activate and the device will

enter the all-off state.

2.10 Temperature Shutdown

The thermal shutdown mechanism will activate when

the device temperature reaches a minimum of 110° C,

placing the device in the all-off state regardless of

logic input. During thermal shutdown mode, the

voltage out of the T

pin will read 0 V. Normal output

of T

is V

If presented with a short duration transient such as a

lightning event, the thermal shutdown feature will

typically not activate. But in an extended power-cross

transient, the device temperature will rise and the

thermal shutdown will activate forcing the switches to

the all-off state. At this point the current measured into

LINE

or R

LINE

will drop to zero. Once the device

enters thermal shutdown it will remain in the all-off

state until the temperature of the device drops below

the deactivation level of the thermal shutdown circuit.

This will permit the device to return to normal

operation. If the transient has not passed, current will

flow up to the value allowed by the dynamic DC

current limiting of the switches and heating will begin

again, reactivating the thermal shutdown mechanism.

This cycle of entering and exiting the thermal

shutdown mode will continue as long as the fault

condition persists. If the magnitude of the fault

condition is great enough, the external secondary

protector could activate and shunt all current to

ground.

2.11 External Protection Elements

The CPC7583 requires only over-voltage secondary

protection on the loop side of the device. The

integrated protection feature described above negates

the need for additional protection on the SLIC side.

The secondary protector must limit voltage transients

to levels that do not exceed the breakdown voltage or

input-output isolation barrier of the CPC7583. A

foldback or crowbar type protector is recommended to

minimize stresses on the CPC7583.

Consult IXYS Integrated Circuits Division’s application

note, AN-100, “Designing Surge and Power Fault

Protection Circuits for Solid State Subscriber

Line Interfaces” for equations related to the

specifications of external secondary protectors, fused

resistors and PTCs.

NTEGRATED

IRCUITS

IVISION

18 www.ixysic.com R07

CPC7583

3 Manufacturing Information

3.1 Moisture Sensitivity

All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated

Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the

latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product

evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee

proper operation of our devices when handled according to the limitations and information in that standard as well as

to any limitations set forth in the information or standards referenced below.

Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced

product performance, reduction of operable life, and/or reduction of overall reliability.

This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to

the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.

3.2 ESD Sensitivity

This product is ESD Sensitive, and should be handled according to the industry standard

JESD-625.

3.3 Reflow Profile

This product has a maximum body temperature and time rating as shown below. All other guidelines of

J-STD-020 must be observed.

3.4 Board Wash

IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to

remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or

Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be

used.

Device Moisture Sensitivity Level (MSL) Rating

CPC7583BA MSL 1

Device Maximum Temperature x Time

CPC7583BA 260°C for 30 seconds

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

CPC7583BATR

Mfr. #:

Buy CPC7583BATR

Manufacturer:

IXYS Integrated Circuits

Description:

Switch ICs - Various 10-pole SOIC LCAS

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

CPC7583BATR

CPC7583BATR

Products related to this Datasheet