9
640220fa
LT6402-20
V
OCM
(Pin 2): This pin sets the output common mode
voltage. Without additional biasing, both inputs bias to
this voltage as well. This input is high impedance.
V
CCA
, V
CCB
, V
CCC
(Pins 3, 10, 1): Positive Power Supply
(Normally Tied to 5V). All three pins must be tied to the
same voltage. Bypass each pin with 1000pF and 0.1µF
capacitors as close to the package as possible. Split
supplies are possible as long as the voltage between V
CC
and V
EE
is 5V.
V
EEA
, V
EEB
, V
EEC
(Pins 4, 9, 12): Negative Power Supply
(Normally Tied to Ground). All three pins must be tied to
the same voltage. Split supplies are possible as long as
the voltage between V
CC
and V
EE
is 5V. If these pins are
not tied to ground, bypass each pin with 1000pF and 0.1µF
capacitors as close to the package as possible.
+OUT, –OUT (Pins 5, 8): Outputs (Unfi ltered). These
pins are high bandwidth, low-impedance outputs. The DC
output voltage at these pins is set to the voltage applied
at V
OCM
.
+OUTFILTERED, –OUTFILTERED (Pins 6, 7): Filtered
Outputs. These pins add a series 50Ω resistor from the
unfi ltered outputs and three 14pF capacitors. Each output
has 14pF to V
EE
, plus an additional 14pF between each pin
(See the Block Diagram). This fi lter has a –3dB bandwidth
of 75MHz.
⎯
E
⎯
N
⎯
A
⎯
B
⎯
L
⎯
E (Pin 11): This pin is a TTL logic input referenced
to the V
EEC
pin. If low, the LT6402 is enabled and draws
typically 30mA of supply current. If high, the LT6402 is
disabled and draws typically 250µA.
+INA, +INB (Pins 15, 16): Positive Inputs. These pins are
normally tied together. These inputs may be DC- or AC-
coupled. If the inputs are AC-coupled, they will self-bias
to the voltage applied to the V
OCM
pin.
–INA, –INB (Pins 14, 13): Negative Inputs. These pins are
normally tied together. These inputs may be DC- or AC-
coupled. If the inputs are AC-coupled, they will self-bias
to the voltage applied to the V
OCM
pin.
Exposed Pad (Pin 17): Tie the pad to V
EEC
(Pin 12). If split
supplies are used, DO NOT tie the pad to ground.
PI FU CTIO S
UUU
+
–
14
INA
5
+OUT
6402 BD
3
V
CCA
10
V
CCB
1
V
CCC
11
ENABLE
13
INB
14pF
V
CCA
A
V
EEA
V
EEA
50Ω
6
+OUTFILTERED
–
+
16
+INA
8
–OUT
15
+INB
V
CCB
B
V
EEB
V
EEB
100Ω
100Ω
100Ω
100Ω
500Ω
500Ω
500Ω
500Ω
50Ω
14pF
14pF
7
–OUTFILTERED
12
V
EEC
9
V
EEB
4
V
EEA
+
–
V
EEC
C
V
CCC
2
V
OCM
BIAS
BLOCK DIAGRA
W