5
Switching Specications
Over recommended temperature (T
A
= –40°C to +105°C), 3.0V ≤ V
DD
≤ 3.6V and 4.5 V ≤ V
DD
≤ 5.5 V.
All typical specications are at T
A
=+25°C, V
DD
= +3.3V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Propagation Delay Time
to Logic Low Output
[2]
t
PHL
25 55 ns I
F
= 6mA, C
L
= 15pF
CMOS Signal Levels
Propagation Delay Time
to Logic High Output
[2]
t
PLH
21 55 ns I
F
= 6mA, C
L
= 15pF,
CMOS Signal Levels
Pulse Width t
PW
66.7 ns
Pulse Width Distortion
[3]
|PWD | 0 4 25 ns I
F
= 6mA, C
L
= 15pF,
CMOS Signal Levels
Propagation Delay Skew
[4]
t
PSK
40 ns I
F
= 6mA, C
L
= 15pF
CMOS Signal Levels
Output Rise Time
(10% – 90%)
t
R
3.5 ns I
F
= 6mA, C
L
= 15pF
CMOS Signal Levels
Output Fall Time
(90% - 10%)
t
F
3.5 ns I
F
= 6mA, C
L
= 15pF
CMOS Signal Levels
Common Mode Transient
Immunity at Logic High Output
[5]
| CMH | 10 15 kV/µs V
CM
= 1000 V, T
A
= 25°C,
I
F
= 0 mA (Figure 18)
30 35 kV/µs Using Avago’s Application Circuit
(Figure 13)
Common Mode Transient
Immunity at Logic Low Output
[6]
| CML | 10 15 kV/µs V
CM
= 1000 V, T
A
= 25°C,
I
F
= 6 mA (Figure 18)
30 35 kV/µs Using Avago’s Application Circuit
(Figure 13)
Package Characteristics
All Typical at T
A
= 25°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Input-Output Insulation I
I-O
1.0 µA 45% RH, t = 5 s
V
I-O
= 3 kV DC,
T
A
= 25°C
Input-Output Momentary
Withstand Voltage
V
ISO
3750 Vrms RH ≤ 50%, t = 1 min.,
T
A
= 25°C
Input-Output Resistance R
I-O
10
12
W
V
I-O
= 500 V dc
Input-Output Capacitance C
I-O
0.6 pF f = 1 MHz, T
A
= 25°C
Notes:
1. Slew rate of supply voltage ramping is recommended to ensure no glitch more than 1V to appear at the output pin.
2. t
PHL
propagation delay is measured from the 50% V
DD
level on the rising edge of the input pulse to the 50% V
DD
level of the falling edge of the V
O
signal. t
PLH
propagation delay is measured from the 50% V
DD
level on the falling edge of the input pulse to the 50% V
DD
level of the rising edge of
the V
O
signal.
3. PWD is dened as |t
PHL
- t
PLH
|.
4. t
PSK
is equal to the magnitude of the worst case dierence in t
PHL
and/or t
PLH
that will be seen between units at any given temperature within the
recommended operating conditions.
5. CM
H
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
6. CM
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
