LTM8050
10
8050fc
For more information www.linear.com/LTM8050
PIN FUNCTIONS
V
OUT
(Bank 1): Power Output Pins. Apply the output filter
capacitor and the output load between these pins and
GND pins.
GND (Bank 2): Tie these GND pins to a local ground plane
below the LTM8050 and the circuit components. In most
applications, the bulk of the heat flow out of the LTM8050
is through these pads, so the printed circuit design has a
large impact on the thermal performance of the part. See
the PCB Layout and Thermal Considerations sections for
more details. Return the feedback divider (R
FB
) to this net.
V
IN
(Bank 3): The V
IN
pin supplies current to the LTM8050’s
internal regulator and to the internal power switch. This
pin must be locally bypassed with an external, low ESR
capacitor; see Table 1 for recommended values.
AUX (Pin G5): Low Current Voltage Source for BIAS. In
many designs, the BIAS pin is simply connected to V
OUT
.
The AUX pin is internally connected to V
OUT
and is placed
adjacent to the BIAS pin to ease printed circuit board rout-
ing. Although
this pin is internally connected to V
OUT
, it
is not intended to deliver a high current, so do not draw
current from
this pin to the load. If this pin is not tied to
BIAS, leave it floating.
BIAS
(Pin H5): The BIAS pin connects to the internal power
bus. Connect to a power source greater than 2.8V and less
than 25V. If the output is greater than 2.8V, connect this
pin there. If the output voltage is less, connect this to a
voltage source between 2.8V and 25V. Also, make sure
that BIAS + V
IN
is less than 72V.
RUN/SS (Pin L5): Pull the RUN/SS pin below 0.2V to
shut down the LTM8050. Tie to 2.5V or more for normal
operation. If the shutdown feature is not used, tie this pin
to the V
IN
pin. RUN/SS also provides a soft-start function;
see the Applications Information section.
SYNC (Pin L6): This is the external clock synchronization
input. Ground this pin for low ripple Burst Mode operation
at low output loads. Tie to a stable voltage source greater
than 0.7V to disable Burst Mode operation. Do not leave
this pin floating. Tie to a clock source for synchroniza
-
tion. Clock edges should have rise and fall times faster
than
s. See the Synchronization section in Applications
Information
.
RT (Pin
G7): The RT pin is used to program the switching
frequency of the LTM8050 by connecting a resistor from
this pin to ground. Table 2 gives the resistor values that
correspond to the resultant switching frequency. Minimize
the capacitance at this pin.
SHARE (Pin H7): Tie this to the SHARE pin of another
LTM8050 when paralleling the outputs. Otherwise, do
not connect.
PGOOD (Pin J7): The PGOOD pin is the open-collector
output of an internal comparator. PGOOD remains low until
the FB pin is within 10% of the final regulation voltage.
PGOOD output is valid when V
IN
is above 3.6V and RUN/SS
is high. If this function is not used, leave this pin floating.
FB (Pin K7): The LTM8050 regulates its FB pin to 0.79V.
Connect the adjust resistor from this pin to ground. The
value of R
FB
is given by the equation R
FB
= 394.21/(V
OUT
– 0.79), where R
FB
is in kΩ.
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM8050
11
8050fc
For more information www.linear.com/LTM8050
BLOCK DIAGRAM
OPERATION
The LTM8050 is a standalone nonisolated step-down
switching DC/DC power supply that can deliver up to 2A of
output current. This module provides a precisely regulated
output voltage programmable via one external resistor
from 0.8V to 24V. The input voltage range is 3.6V to 58V.
Given that the LTM8050 is a step-down converter, make
sure that the input voltage is high enough to support the
desired output voltage and load current.
As shown in the Block Diagram, the LTM8050 contains a
current mode controller, power switching element, power
inductor, power Schottky diode and a modest amount of
input and output capacitance. The LTM8050 is a fixed
frequency PWM regulator. The switching frequency is set
by simply connecting the appropriate resistor value from
the RT pin to GND.
An internal regulator provides power to the control circuitry.
The bias regulator normally draws power from the V
IN
pin, but if the BIAS pin is connected to an external volt-
age higher than 2.8V, bias power will be drawn from the
external
source (typically the regulated output voltage).
This improves efficiency. The RUN/SS pin is used to place
the LTM8050 in shutdown, disconnecting the output and
reducing the input current to less than 1μA.
To further optimize efficiency, the LTM8050 automatically
switches to Burst Mode
®
operation in light load situations.
Between bursts, all circuitry associated with controlling
the output switch is shut down reducing the input supply
current to 50μA in a typical application.
The oscillator reduces the LTM8050’s operating frequency
when the voltage at the FB pin is low. This frequency fold
-
back helps to control the output current during start-up
and overload.
The LTM8050 contains a power good comparator which
trips when the FB pin is at roughly 90% of its regulated
value. The PGOOD output is an open-collector transistor
that is off when the output is in regulation, allowing an
external resistor to pull the PGOOD pin high. Power good is
valid when the LTM8050 is enabled and V
IN
is above 3.6V.
The LTM8050 is equipped with a thermal shutdown that
will inhibit power switching at high junction tempera-
tures. The activation threshold of this function, however,
is above 125°C to avoid interfering with normal operation.
Thus, prolonged or repetitive operation under a condition
in which the thermal shutdown activates may damage or
impair the reliability of
the device.
8050 BD
V
IN
8.2µH
4.4µF0.2µF
CURRENT
MODE
CONTROLLER
RUN/SS
SHARE
SYNC
AUX
BIAS
GND RT FBPGOOD
V
OUT
15pF
499k
1%
LTM8050
12
8050fc
For more information www.linear.com/LTM8050
APPLICATIONS INFORMATION
For most applications, the design process is straight
forward, summarized as follows:
1. Look at Table 1 and find the row that has the desired
input range and output voltage.
2. Apply the recommended C
IN
, C
OUT
, R
FB
and R
T
values.
3. Connect BIAS as indicated.
While these component combinations have been tested
for proper operation, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions. Bear in mind that the
maximum output current is limited by junction tempera-
ture, the relationship between the input and output voltage
magnitude and polarity and other factors. Please refer to
the graphs in the Typical Performance Characteristics
section for guidance.
The maximum frequency (and attendant R
T
value) at
which the LTM8050 should be allowed to switch is given
in Table 1 in the f
MAX
column, while the recommended
frequency (and R
T
value) for optimal efficiency over the
given input condition is given in the f
OPTIMAL
column.
There are additional conditions that must be satisfied if
the synchronization function is used. Please refer to the
Synchronization section for details.
Capacitor Selection Considerations
The C
IN
and C
OUT
capacitor values in Table 1 are the
minimum recommended
values for the associated oper-
ating conditions.
Applying capacitor values below those
indicated in Table 1 is not recommended, and may result
in undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response, if
it is necessary. Again, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions.
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable.
X5R and X7R types are stable over temperature and ap
-
plied voltage
and give dependable service. Other types,
including Y5V and Z5U have very large temperature and
voltage coefficients of capacitance. In an application cir
-
cuit they may have only a small fraction of their nominal
capacitance resulting in much higher output voltage ripple
than expected.
Ceramic capacitors are also piezoelectric. In Burst Mode
operation, the LTM8050’s switching frequency depends
on the load current, and can excite a ceramic capacitor
at audio frequencies, generating audible noise. Since the
LTM8050 operates at a lower current limit during Burst
Mode operation, the noise is typically very quiet to a
casual ear.
If this audible noise is
unacceptable, use
a high perfor-
mance electrolytic
capacitor at the output. It may also be
a parallel combination of a ceramic capacitor and a low
cost electrolytic capacitor.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8050. A
ceramic input capacitor combined with trace or cable
inductance forms a high Q (under damped) tank circuit.
If the LTM8050 circuit is plugged into a live supply, the
input voltage can ring to twice its nominal value, possi
-
bly exceeding the device’s rating. This situation is easily
avoided; see the Hot-Plugging Safely section.
Frequency Selection
The LTM8050 uses a constant frequency PWM architec-
ture that can be programmed to switch from 100kHz to
2.4MHz by using a resistor tied from the RT pin to ground.
Table 2 provides a list of R
T
resistor values and their re-
sultant frequencies.

LTM8050MPY#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 58V, 2A Buck Module Reg
Lifecycle:
New from this manufacturer.
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